A 16-kbit Block Addressed Charge-Coupled Memory Device

Charge coupled devices (CCD) have several advantages over tube camera imaging devices. These advantages include: geometric stability, high dynamic range (12, 14, or 16 bits) and photometric linearity. In order to achieve low-readout noise the readout is usually limited to 50 kpixels per second. The readout time is several times longer than video rates; the slow readout at less than video rates is the major disadvantage. A new CCD imager has been coupled to a Nipkow disk, confocal light microscope and its performance is evaluated using both reflected light and low-light-level fluorescence imaging. The CCD imager is a TK515, silicon CCD which is sensitiveequalsve from the UV to the near-IR. The sensor is a full frame area imager, with CCDs fabricated using a buried channel, three-level polysilicon gate process with very high charge-transfer efficiency (>0.9999) and low dark current. Low noise on-chip amplifiers provide and interface to external preamplifiers with readout noise typically <10 electrons at -90 degree(s) C, and 50 kpixels/second data rate. The chip is a thinned, back-illuminated device with anti-reflection coatings. The quantum efficiency is >80% at 400 nm and >90% at 600 nm. To determine its performance the Tektronix CCD was mounted in a Photometrics liquid cooled camera, attached to a Technical Instruments K2Bio confocal microscope.

The frame transfer Area Array Sensor with vertical antiblooming structure requires that all performance characteristics such as large charge capacity, high charge transfer efficiency, low read noise and low antiblooming voltage be optimized in a singlemanufacturable CCD (charge-coupled device). There is a common tendency to optimize one performance characteristic at the expense of others. With the goal of optimizing above all performance characteristics, a frame transfer area array sensors with vertical antiblooming structure is optimization designed by the CAD (computer aided design) tools and fabricated, which equal to twenty-six micron square pixel size with 516 (H) x1028 (V) active pixels(the channel stop is 4&mu;m and the photosensitive area is 22x22 &mu;mx&mu;m). At first, it is simply introduced the modeling of the frame transfer area array sensors with vertical antiblooming structure from the top to down and simulated by the CAD tools combined with the process and device models. The essential design and calculation of the CCD with antiblooming function are discussed in detail. And the process, layout and device parameters to design this frame transfer area array sensors (including the impurity concentration and layer thickness of the P-well and the buriedchannel, and the design output amplifier) are optimized according to the above simulation. At the last, the device is fabricated and the performance characteristics ( e.g. charge capacity, charge transfer efficiency, read noise and antiblooming voltage) are test to compare the simulation. To demonstrate the process used to optimize this frame transfer area array sensors with vertical antiblooming structure, this paper contains test data for this kind of CCD device which is optimization designed and fabricated by the CAD (computer aided design) tools. The test datas shows the way using the CAD tools optimization design a frame transfer area array sensors with vertical antiblooming structure correct.

Previous studies investigated the usability of charge-coupled devices (CCDs) in the context of economies to be achieved in main memory capacity. In systems with virtual memories, such economies result from the use of fast paging devices. In spite of the concomitant savings in main memory costs, which will probably be eaten up by the costs of the new-technology paging device, the price/performance ratio must be expected to be less favorable than that of conventional systems, since the share of the operating system software required for page fault handling will increase.More recent research has shown, however, that not only the degree of multiprogramming, i.e., the number of processes required to cover an I/O time interval, is a factor of crucial importance for optimum CPU utilization, but also the number of disk devices available in the secondary-storage system: unless the number of storage devices is large enough to handle, within an I/O time interval, at least as many parallel I/O operations as are needed to ensure that a sufficient number of processes are again ready for busying the CPU, the aim of full utilization of the CPU cannot be achieved---not even through a higher degree of multiprogramming. With disk devices of ever higher recording densities but otherwise nearly constant performance data becoming available, fewer devices than today will be required in the future to store the on-line data file volume. Since fast, favorably priced central processing units are likewise becoming available, it must be expected that the future systems, unlike the systems of today, will for the first time be beset with the problem of input/output bottlenecks arising from an insufficient number of storage devices. Rather than attempting to achieve the required I/O data rate through a sufficient number of devices operating in parallel, use should therefore be made of such devices as CCD storages in secondary-storage hierarchies, which offer themselves as the less costly solution to the problem.

The laser confocal microscope (LCM) is now an established research tool in biology and materials science. In biological applications, it is usually employed to detect the location of fluorescent market molecules and, under these conditions, signal levels from bright areas are often < 20 photons/pixel (from the specimen, assuming a standard 512 X 768, 1 sec. scan). Although this data rate limits the speed at which information can be derived from the specimen, saturation of the fluorophor, photobleaching of the dye, and phototoxicity prevent it being increased. Currently, most LCMs use photomultiplier tubes (PMT, QE equals 1 - 30% 400 - 900 nm). By contrast, rear-illuminated, scientific charge-coupled devices (CCD) now routinely readout the signal from square sensors approximately 30 micrometers on a side with a QE of 80 - 90%, a noise of only +/- 3 e-/pix and with no multiplicative noise. For this reason, in 1989, one of us (JJ) developed a rear-illuminated, single-channel Si sensor, called the Turbodiode, employing some of the sophisticated readout techniques used to measure charge in a scientific CCD. We are now extending this work to a device in which a single 36 X 36 micrometers sensor is read out through a low-noise FET charge amplifier with a reset circuit and then passed to a correlated, double-sampling digitizer. To maintain the desired +/- 3 e noise level at the relatively high data rate of 1 MHz, our new device utilizes 64 separate readout amplifier/digitizer systems, operating in sequence. The resulting detector is more compact, efficient and reliable than the PMT it replaces but as its sensitive area is smaller than that of a PMT, it will require auxiliary optics when used with any LCM having a large (mm) pinhole. As the signal light is parallel, a simple lens mounted axially and with the CCDiode at its focus would suffice. Future versions may use 3 X 3 or 5 X 5 arrays of sensors to `track' the confocal spot as it is deflected by inhomogeneities of the specimen, change its effective size or shape or detect system misalignment.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In mid-2019, the SuperCam instrument was installed aboard NASA's Mars 2020 rover, which is scheduled for launch in July 2020 and a landing at Jezero crater in February 2021. SuperCam is a collaboration between Los Alamos National Laboratory (LANL; the lead institution) and the Institut de Recherche en Astrophysique et Planetologie (IRAP), funded by the French Space Agency (CNES) and with contributions by universities and laboratories in France, Spain, and Denmark. SuperCam integrates a number of observation techniques into a single instrument, which builds on the design heritage of ChemCam, a laser induced breakdown spectroscopy (LIBS) instrument aboard the Curiosity rover. While retaining ChemCam's LIBS mode, SuperCam adds a remote Raman spectroscopy mode, an infrared spectrometer (IR), a microphone, and improves upon ChemCam's greyscale context imager with a color imager. This paper will give a broad overview of the SuperCam instrument, which is divided into three portions: the LANL-built SuperCam Body Unit (SCBU), the French-built SuperCam Mast Unit (SCMU), and the Spanish-built SuperCam Calibration Target (SCCT). The instrument operational modes will be detailed, explaining how the instrument as a whole is used to collect and process its data within the context of the Mars 2020 rover. Next, we will detail LANL's design, integration, and testing of the SCBU. The SCBU is installed inside the rover's body and features an optical demultiplexer feeding a set of three spectrometers, which are digitized by three charge-coupled devices (CCDs) from e2v, controlled by a low-noise spectrometer electronics module. The longest-wavelength visible-range spectrometer employs high-throughput transmission optics and an image intensifier to amplify and electronically gate the incoming light in Raman mode. This transmission spectrometer is powered and controlled by a high voltage power supply, designed and built at LANL. A low voltage power supply converts rover power to voltages used by the instrument. The command and data handling (C&DH) module features a Leon-3-based processor and a field programmable gate array for custom logic, along with a memory array. Instrument flight software architecture will be presented, with a focus on the body unit and mast unit functionality divide. The test qualification scheme will be detailed, with information on instrument optical performance testing.

Charge transfer device (CTD) detectors consist of two closely related silicon integrated circuits: the charge-coupled device (CCD), invented in 1970, and the charge injection device (CID), invented in 1973. Initially, several applications were proposed for these integrated circuits, including use as shift registers, logic and memory devices, electronic delay lines, and imaging detectors. The last application has so dominated the design and use of CTDs that they are among the most common electronic imaging detectors manufactured today.

Lateral profiling of interface states along the sidewalls of channel-stop isolation

Very-long-baseline interferometry (VLBI) is a type of astronomical interferometry used in radio astronomy. VLBI digital backend is a wideband data acquisition system with dedicated real time data processing algorithms implemented and installed in each VLBI station. The VLBI institutes in American, Europe, Japan and China have start to develop VLBI digital backends in 2000s. The first VLBI digital backend named Chinese VLBI Data Acquisition System (CDAS) developed by Shanghai Astronomical Observatory (SHAO) was finished in 2009. It has four intermediate frequency (IF) input channels with 512 MHz bandwidth for each. After processing, the output data rate is up to about 2048 Mbps. CDAS has begun to serve for Chinese Lunar Project in Chinese VLBI Network (CVN) stations in 2010. Since 2013, another type of VLBI digital backend has been designed in order to meet the requirement of VLBI Global Observation System (VGOS), it was named CDAS2. Comparing with CDAS, CDAS2 not only doubles the number of input channels but also makes the 10-Gigabit Ethernet (10GE) interface available. Due to the different algorithms implemented, the output data rate of CDAS2 is up to about 16384 Mbps. It will be installed in Sheshan VGOS station this year. Furthermore, CDAS3 has been put on the schedule. It will double the bandwidth of each IF channel and the maximum data rate of output, comparing with CDAS2. It is prepared for the next stage of VGOS, which need 1024 MHz bandwidth input for each channel and 32768 Mbps maximum data rate output. In this article, we will introduce these digital backends in detail including the hardware and algorithm. And also comparisons will be made.

This paper presents a precision wide range Delta Sigma ADC SC1601 (SC1601 is the product number of ADC) with programmable gain amplifier (PGA) and programmable output data rate features. The ADC offers four fully differential input channels. Each channel can be programmed with a gain of 1 to 128 in binary steps i.e. in powers of 2. The ADC uses a second order delta sigma modulator (DSM) followed by a digital sinc\(^3\) filter. The output data rate of the ADC is also programmable from 312.5 Hz to 2.5 kHz either to achieve higher accuracy or higher speed. The ADC also offers on chip offset and gain calibration features to reduce the offset and gain errors. The serial interface of ADC is SPI\(^{TM}\) compatible. The SC1601 ADC is fabricated in 0.18 \(\upmu \)m CMOS process at Semi-Conductor Laboratory (SCL). The total power consumption of the ADC is 4 mW and it consumes total silicon area of 2.25 mm\(^2\). SC1601 ADC achieves a maximum ENOB of 19.15 bits at a data rate of 312.5 Hz with a full scale range of 1.22 V. The ADC requires a supply voltage of 3.3 V and 1.8 V and can operate in a wide temperature range of −55\(^{\circ }\)C to 125\(^{\circ }\)C. SC1601 ADC is developed for the satellite launch vehicle telemetry system.KeywordsDelta sigma modulatorAnalog multiplexerProgrammable gain amplifierDigital filter

A computerized perceptual laboratory operates a variety of stimulus devices, including static and dynamic graphics displays, and records both discrete and analog data in a diverse and complex set of experimental paradigms. The software requirement to accommodate this variety of paradigms and high input and output data rates has been met by a single multitasked acquisition program that interprets unitary event commands to display graphics or nongraphics stimuli, record responses, control timing, or provide appropriate feedback. Event lists are created and modified with a text editor, then assembled into binary experiment definition files by dialogue with a parsing program. Graphics stimuli are referenced by a file name that contains stimulus attributes for later data extraction. All protocols and stimulus files are loaded prior to the block of trials, so no disk accesses that would delay events are required during a block. The resulting data file contains a record of all variable stimulus and timing information, as well as the discrete and analog responses, in a uniform format which facilitates data extraction.

Recently, metal halide perovskites have been widely used and considered as an alternative to oxides or chalcogenides in memory devices due to the high on–off ratio and low operating voltage, as well as ease of fabrication. However, most of the perovskite thin films in previous studies have been deposited by lab‐scale solution‐processed methods. They are not directly applicable to larger‐scale and volume manufacturing, hindering the commercialization of this technology. Herein, the performance of memory devices based on vacuum‐deposited inorganic perovskite (VDIP) is investigated for the first time. The optimized VDIP‐based memory devices exhibit reliable and reproducible resistive switching (RS) behaviors with a high on–off ratio (&gt;100), low set/reset voltage (&lt;2 V), and reversible RS by fast pulse‐voltage operations. Furthermore, the devices show an excellent ambient stability, and no obvious degradation is observed after storage in an ambient condition for 30 days. The memory devices on flexible substrates also show a good mechanical flexibility under a bending stress. In addition, a VDIP memory array with 16 × 16 memory cells on a large‐scale substrate is demonstrated, suggesting the strong potential of the VDIP for high‐density, large‐area storage devices.

High-speed imaging is an indispensable technique, particularly for identifying or analyzing fast-moving objects. The serial time-encoded amplified microscopy (STEAM) technique was proposed to enable us to capture images with a frame rate 1,000 times faster than using conventional methods such as CCD (charge-coupled device) cameras. The application of this high-speed STEAM imaging technique to a real-time system, such as flow cytometry for a cell-sorting system, requires successively processing a large number of captured images with high throughput in real time. We are now developing a high-speed flow cytometer system including a STEAM camera. In this paper, we describe our approach to processing these large amounts of image data in real time. We use an analog-to-digital converter that has up to 7.0G samples/s and 8-bit resolution for capturing the output voltage signal that involves grayscale images from the STEAM camera. Therefore the direct data output from the STEAM camera generates 7.0G byte/s continuously. We provided a field-programmable gate array (FPGA) device as a digital signal pre-processor for image reconstruction and finding objects in a microfluidic channel with high data rates in real time. We also utilized graphics processing unit (GPU) devices for accelerating the calculation speed of identification of the reconstructed images. We built our prototype system, which including a STEAM camera, a FPGA device and a GPU device, and evaluated its performance in real-time identification of small particles (beads), as virtual biological cells, owing through a microfluidic channel.

Optoelectronic devices are advantageous in in-memory light sensing for visual information processing, recognition, and storage in an energy-efficient manner. Recently, in-memory light sensors have been proposed to improve the energy, area, and time efficiencies of neuromorphic computing systems. This study is primarily focused on the development of a single sensing-storage-processing node based on a two-terminal solution-processable MoS2 metal–oxide–semiconductor (MOS) charge-trapping memory structure—the basic structure for charge-coupled devices (CCD)—and showing its suitability for in-memory light sensing and artificial visual perception. The memory window of the device increased from 2.8 V to more than 6 V when the device was irradiated with optical lights of different wavelengths during the program operation. Furthermore, the charge retention capability of the device at a high temperature (100 °C) was enhanced from 36 to 64% when exposed to a light wavelength of 400 nm. The larger shift in the threshold voltage with an increasing operating voltage confirmed that more charges were trapped at the Al2O3/MoS2 interface and in the MoS2 layer. A small convolutional neural network was proposed to measure the optical sensing and electrical programming abilities of the device. The array simulation received optical images transmitted using a blue light wavelength and performed inference computation to process and recognize the images with 91% accuracy. This study is a significant step toward the development of optoelectronic MOS memory devices for neuromorphic visual perception, adaptive parallel processing networks for in-memory light sensing, and smart CCD cameras with artificial visual perception capabilities.

Charge exchange spectroscopy is one of the key ion diagnostics on the DIII-D tokamak. It allows determination of ion temperature, poloidal and toroidal velocity, impurity density, and radial electric field Er throughout the plasma. For the 2003 experimental campaign, we replaced the intensified photodiode array detectors on the central portion of the DIII-D charge exchange spectroscopy system with advanced charge–coupled device (CCD) detectors mounted on faster (f/4.7) Czerny–Turner spectrometers equipped with toroidal mirrors. The CCD detectors are improved versions of the ones installed on our edge system in 1999. The combination improved the photoelectron signal level by about a factor of 20 and the signal to noise by a factor of 2–8, depending on the absolute signal level. The new cameras also allow shorter minimum integration times while archiving to PC memory: 0.552 ms for the slower, lower-read noise (15 e) readout mode and 0.274 ms in the faster, higher-read noise (30 e) mode.

ABSTRACTMFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 – 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 – 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties.