CPU-utilization and secondary-storage performance

The diffusion space of data diffusion architectures

This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memory or as a hardware-managed cache. Using stacked DRAM as part of main memory increases the effective capacity, but obtaining high performance from such a system requires Operating System (OS) support to migrate data at a page-granularity. Using stacked DRAM as a hardware cache has the advantages of being transparent to the OS and perform data management at a line-granularity but suffers from reduced main memory capacity. This is because the stacked DRAM cache is not part of the memory address space. Ideally, we want the stacked DRAM to contribute towards capacity of main memory, and still maintain the hardware-based fine-granularity of a cache. We propose CAMEO, a hardware-based Cache-like Memory Organization that not only makes stacked DRAM visible as part of the memory address space but also exploits data locality on a fine-grained basis. CAMEO retains recently accessed data lines in stacked DRAM and swaps out the victim line to off chip memory. Since CAMEO can change the physical location of a line dynamically, we propose a low overhead Line Location Table (LLT) that tracks the physical location of all data lines. We also propose an accurate Line Location Predictor (LLP) to avoid the serialization of the LLT look-up and memory access. We evaluate a system that has 4GB stacked memory and 12GB off-chip memory. Using stacked DRAM as a cache improves performance by 50%, using as part of main memory improves performance by 33%, whereas CAMEO improves performance by 78%. Our proposed design is very close to an idealized memory system that uses the 4GB stacked DRAM as a hardware-managed cache and also increases the main memory capacity by an additional 4GB.

Main memory virtualization is used to expand the effective main memory capacity meaning that more virtual main memory is represented to guest operating systems than physical memory is actually available. This is done by compressing and uncompressing memory pages. Obviously the price for main memory virtualization is a higher CPU utilization, especially when dealing with high workloads. SAP ERP systems represent the backbone of today's enterprises and have a very high resource demand. The combination of main memory virtualization and SAP ERP system is of great importance but has not yet been thoroughly researched. This paper is the first approach to a quantitative research for evaluating the performance impact of memory virtualization on SAP ERP systems. We utilize a synthetic main memory benchmark, called Zachmanntest, to evaluate the performance impact of main memory virtualization on a SAP ERP system. As an exemplary main memory virtualization implementation IBM's Active Memory Expansion is used, where a so called expansion factor can be used to specify the size of the virtual main memory. Performance results show that the greater the expansion factor, the greater the performance impact. Regarding the peak performance, throughput of SAP ERP systems may be decreased till -17%, whereas the overall throughput of such systems may experience a decrease up to -42% when dealing with a very high compression factor.

This paper describes the design and performance of a 16-kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 /spl mu/W/bit with another 0.5 /spl mu/W/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.

Heterogeneous computing utilizing both CPU and FPGA requires access to data in the main memory from both devices. While a typical system relies on software executing on the CPU to orchestrate all data movements between the FPGA and the main memory, our demo presents a complementary FPGA-centric approach that allows gateware to directly access the virtual memory space as part of the executing process without involving the CPU. A caching address translation buffer was implemented alongside the user FPGA gateware to provide runtime mapping between virtual and physical memory addresses. The system was implemented on a commercial off-the-shelf FPGA add-on card to demonstrate the viability of such approach in low-cost systems. Experiment demonstrated reasonable performance improvement when compared to a typical software-centric implementation; while the number of context switches between FPGA and CPU in both kernel and user mode was significantly reduced, freeing the CPU for other concurrent user tasks.

A non-contact rain gauge with photo electricity technology is introduced in this paper. Dimensional distribution of rain inside a traditional rain gauge does not need to be changed, and the rainwater falls freely to the ground, so this new rain gauge doesn't need to be cleared as a traditional rain gauge does frequently. And then a capacitor is used as a switch that would drive LED light to scan and drive photo electricity inducing element Charge Coupled Device (CCD) to detect when it is induced by the falling drips. Light through a convex lens would scan the drips and project them on CCD across. Electrical signal is produced when CCD detects the shadow after another convex lens. The drips whose diameter is 0.3 millimeter can be distinguished and so as smaller drips of 0.1 millimeter if high-resolution CCD is used. After an amplifier the electrical signal would be transformed into digital signal and would be used to calculate the volume of rain. The Central Processing Unit on main control board gives commands to scanning trigger and controls interrupts from process of data acquisition and calculation. The non-contact photo electricity measurement can detect raindrops of different size. Parallel light projects every raindrop in space on CCD and tells its diameter exactly. So it gives satisfying precision and other useful data such as spectrum of raindrops. Further more, velocity of raindrop would be acquired according to its size. The system needs low cost with universal CCD and Single Chip Micyoco (SCM), and it is worth advocating.

A high-performance image processing system (HIPS) has been developed to provide two- dimensional image acquisition for a variety of opti- cal applications. The system is built around two high-performance visible-light charged coupled device(CCD) arrays: a 32-port, 1024 x 1024 pixel array anda 16-port, 512 x 512 pixel array. The arrays and as- sociated circuitry were designed to operate at high frame rates, with an optical power dynamic range ofover 30 dB. The 512 x 512 array is designed to operateat over 800 frames per second; the larger device, atover 300 frames per second. The system has two main units: a stand-alone high-performance camera array module (HPCAM)and a VME-based image capture and display system(ICADS). HPCAM contains a CCD array and associ-ated drive and control electronics. ICADS consists ofan analog multiplexer, digitizer, digital frame buffer-integrator, main central processing unit (CPU) board with user and Ethernet interfaces, graphics driver, and high-resolution monitor.The CCD arrays used in this work are designed foruse in optical processing systems, such as radar ambi-guity, wide-band signal detection, and synthetic aper-ture radar (SAR) image formation processors. Thissystem provides a method for capturing and display-ing CCD array output data, giving the researcher amethod to analyze and develop CCD array and opti-cal processing systems.

Searching for elements in a dataset that are similar to a given query element is a core problem in applications that use complex data, and has been carried out aided by a metric access method (MAM). A growing number of these applications require indices that can be built faster and for several times, in addition to providing smaller response times for similarity queries. Besides, the increase in the main memory capacity and its lowering costs also motivate using memory-based MAMs. In this paper, we propose the Onion-tree , a new and robust dynamic memory-based MAM that performs a hierarchical division of the metric space into disjoint subspaces. The Onion-tree is very compact, requiring a small fraction of the main memory (e.g., at most 4.8%). Comparisons of the Onion-tree , a memory-based version of the Slim-tree, and the memory-based MM-tree showed that the Onion-tree always produced the smallest elapsed time to build the index. Our experiments also showed that the Onion-tree produced the best query performance results, followed by the MM-tree, which in turn outperformed the Slim-tree. With regard to the MM-tree, the Onion-tree provided a reduction in the number of distance calculations that ranged from 1% to 11% in range queries and from 16% up to 64% in k -NN queries. The Onion-tree also significantly improved the required elapsed time, which ranged from 12% to 39% in range query processing and from 40% up to 70% in k -NN query processing, as compared to the MM-tree, its closest competitor. The Onion-tree source code is available at http://gbd.dc.ufscar.br/download/Onion-tree .

In the big data era, a huge number of services has placed a fast-growing demand on the capacity of DRAM-based main memory. However, due to the high hardware cost and serious leakage power/energy consumption, the growth rate of DRAM capacity cannot meet the increased rate of the required main memory space when the energy or hardware cost is a critical concern. To tackle this issue, hybrid main-memory devices/modules have been proposed to replace the pure DRAM main memory with a hybrid main memory module that provides a large main memory space by integrating a small-sized DRAM and a large-sized non-volatile memory (NVM) into the same memory module. Although NVMs have high-density and low-cost features, they suffer from the low read/write performance and low endurance issue, compared to DRAM. Thus, inside the hybrid main-memory module, it also includes a memory management design to use DRAM as the cache of NVMs to enhance its performance and lifetime. However, it also introduces new design challenges in both the OS and the memory module. In this work, we rethink the interactivity of OS and hybrid main-memory module, and propose a cross-layer cache design that (1) utilizes the information from the operating system to optimize the hit ratio of the DRAM cache inside the memory module, and (2) takes advantage of the bulk-size (or block-based) read/write feature of NVM to minimize the time overhead on the data movement between DRAM and NVM. At the same time, this cross-layer cache design is very lightweight and only introduces limited runtime management overheads. A series of experiments was conducted to evaluate the effectiveness of the proposed cross-layer cache design. The results show that the proposed design could improve access performance for up to 88%, compared to the investigated well-known page replacement algorithms.

Charge coupled devices (CCD) have several advantages over tube camera imaging devices. These advantages include: geometric stability, high dynamic range (12, 14, or 16 bits) and photometric linearity. In order to achieve low-readout noise the readout is usually limited to 50 kpixels per second. The readout time is several times longer than video rates; the slow readout at less than video rates is the major disadvantage. A new CCD imager has been coupled to a Nipkow disk, confocal light microscope and its performance is evaluated using both reflected light and low-light-level fluorescence imaging. The CCD imager is a TK515, silicon CCD which is sensitiveequalsve from the UV to the near-IR. The sensor is a full frame area imager, with CCDs fabricated using a buried channel, three-level polysilicon gate process with very high charge-transfer efficiency (>0.9999) and low dark current. Low noise on-chip amplifiers provide and interface to external preamplifiers with readout noise typically <10 electrons at -90 degree(s) C, and 50 kpixels/second data rate. The chip is a thinned, back-illuminated device with anti-reflection coatings. The quantum efficiency is >80% at 400 nm and >90% at 600 nm. To determine its performance the Tektronix CCD was mounted in a Photometrics liquid cooled camera, attached to a Technical Instruments K2Bio confocal microscope.

During recent years, big data explosion and the increase in main memory capacity, on the one hand, and the need for faster data processing, on the other hand, have caused the development of various in-memory processing tools to manage and analyze data. Engaging the speed of the main memory and advantaging data locality, these tools can process a large amount of data with high performance. Apache Ignite, as a distributed in-memory platform, can process massive volumes of data in parallel. Currently, this platform is CPU-based and does not utilize the GPU’s processing resources. To address this concern, we introduce Ignite-GPU that uses the GPU’s massively parallel processing power. Ignite-GPU handles a number of challenges in integrating GPUs into Ignite and utilizes the GPU’s available resources. We have also identified and eliminated time-consuming overheads and used various GPU-specific optimization techniques to improve overall performance. Eventually, we have evaluated Ignite-GPU with the Genetic Algorithm, as a representative of data and compute-intensive algorithms, and gained more than thousands of times speedup in comparison with its CPU version.

Virtual memory was developed to automate the movement of program code and data between main memory and secondary storage to give the appearance of a single. This technique greatly simplified the programmer’s job, particularly when program code and data exceeded the main memory’s size. In modern operating system, secure file system can protect confidential data from unauthorized access. However, once an authorized process has accessed data from a cryptographic file system, the data can appear as plaintext in the unprotected virtual memory backing store, even after system shutdown. This paper proposes new approach for adding multilevel security capability to virtual memory management. It uses partial swap encryption based on process’s security policy. Volatile encryption keys are chosen randomly, and remain valid only for short time periods. Performance comparison shows the total overhead of proposed method.

The laser confocal microscope (LCM) is now an established research tool in biology and materials science. In biological applications, it is usually employed to detect the location of fluorescent market molecules and, under these conditions, signal levels from bright areas are often < 20 photons/pixel (from the specimen, assuming a standard 512 X 768, 1 sec. scan). Although this data rate limits the speed at which information can be derived from the specimen, saturation of the fluorophor, photobleaching of the dye, and phototoxicity prevent it being increased. Currently, most LCMs use photomultiplier tubes (PMT, QE equals 1 - 30% 400 - 900 nm). By contrast, rear-illuminated, scientific charge-coupled devices (CCD) now routinely readout the signal from square sensors approximately 30 micrometers on a side with a QE of 80 - 90%, a noise of only +/- 3 e-/pix and with no multiplicative noise. For this reason, in 1989, one of us (JJ) developed a rear-illuminated, single-channel Si sensor, called the Turbodiode, employing some of the sophisticated readout techniques used to measure charge in a scientific CCD. We are now extending this work to a device in which a single 36 X 36 micrometers sensor is read out through a low-noise FET charge amplifier with a reset circuit and then passed to a correlated, double-sampling digitizer. To maintain the desired +/- 3 e noise level at the relatively high data rate of 1 MHz, our new device utilizes 64 separate readout amplifier/digitizer systems, operating in sequence. The resulting detector is more compact, efficient and reliable than the PMT it replaces but as its sensitive area is smaller than that of a PMT, it will require auxiliary optics when used with any LCM having a large (mm) pinhole. As the signal light is parallel, a simple lens mounted axially and with the CCDiode at its focus would suffice. Future versions may use 3 X 3 or 5 X 5 arrays of sensors to `track' the confocal spot as it is deflected by inhomogeneities of the specimen, change its effective size or shape or detect system misalignment.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In this paper, we propose a software shared virtual memory (SVM) system for heterogeneous multicore accelerator clusters with explicitly managed memory hierarchies. The target cluster consists of a single manager node and many compute nodes. The manager node contains a generalpurpose processor and larger main memory, and each compute node contains a heterogeneous multicore processor and smaller main memory. These nodes are connected with an interconnection network, such as Gigabit Ethernet. The heterogeneous multicore processor in each compute node consists of a general-purpose processor element (GPE) and multiple accelerator processor elements (APEs). The GPE runs an OS and the multiple APEs are dedicated to compute-intensive workloads. The GPE is typically backed by a deep on-chip cache hierarchy and hardware cache coherence. On the other hand, the APEs have small explicitly-addressed local memory instead of caches. This APE local memory is not coherent with the main memory. Different main and local memory units in the accelerator cluster can be viewed as an explicitly managed memory hierarchy: global memory, node local memory, and APE local memory. Since coherence protocols of previous software SVM proposals cannot effectively handle such a memory hierarchy, we propose a new coherence and consistency protocol, called hierarchical centralized release consistency (HCRC). Our software SVM system is built on top of HCRC and software-managed caches. We evaluate the effectiveness and analyze the performance of our software SVM system on a 32-node heterogeneous multicore cluster (a total of 192 APEs).

In recent years, as performance and capacity of main and external memory grow, performance of database management systems (DBMSes) on certain kinds of queries is more determined by raw CPU speed. Currently, PostgreSQL uses the interpreter to execute SQL queries. This yields an overhead caused by indirect calls to handler functions and runtime checks, which could be avoided if the query were compiled into native code "on-the-fly", i.e. just-in-time (JIT) compiled: at run time the specific table structure is known as well as data types and built-in functions used in the query as well as the query itself. This is especially important for complex queries, performance of which is CPU-bound. We’ve developed a PostgreSQL extension that implements SQL query JIT compilation using LLVM compiler infrastructure. In this paper we show how to implement JIT compilation to speed up sequential scan operator (SeqScan) as well as expressions in WHERE clauses. We describe some important optimizations that are possible only with dynamic compilation, such as precomputing tuple attributes offsets only for attributes used by the query. We also discuss the maintainability of our extension, i.e. the automation for translating PostgreSQL backend functions into LLVM IR, using the same source code both for our JIT compiler and the existing interpreter. Currently, with LLVM JIT we achieve up to 5x speedup on synthetic tests as compared to original PostgreSQL interpreter.