Performance of SAP ERP with memory virtualization using IBM active memory expansion as an example

The article discusses the use of an intelligent Power Query system for processing data from SAP ERP. When used with SAP ERP data, Power Query can greatly simplify the data analysis process, as well as improve the accuracy and reliability of results. The article provides an overview of the main features of Power Query and how they can be used for data processing in conjunction with the SAP ERP system. It highlights the benefits of using Power Query, including speeding up data processing time, improving data accuracy, and the ability to easily exchange and reuse data processing procedures. Using Power Query to process and analyze bank statements via SAP ERP provides many advantages. Power Query's powerful data processing and transformation capabilities enable organizations to analyze their financial data quickly and accurately, making it easier to identify trends, improve decision-making and stimulate business growth. In addition, the integration of Power Query with SAP ERP provides organizations with a centralized representation of financial data in real time, which allows them to make informed decisions and optimize their activities. Using Power Query to analyze bank statements can also help organizations reduce manual data processing and minimize the risk of errors, increasing the accuracy and reliability of financial information. In general, Power Query offers a powerful solution for organizations seeking to optimize financial analysis processes and ensure business success.

Heterogeneous computing utilizing both CPU and FPGA requires access to data in the main memory from both devices. While a typical system relies on software executing on the CPU to orchestrate all data movements between the FPGA and the main memory, our demo presents a complementary FPGA-centric approach that allows gateware to directly access the virtual memory space as part of the executing process without involving the CPU. A caching address translation buffer was implemented alongside the user FPGA gateware to provide runtime mapping between virtual and physical memory addresses. The system was implemented on a commercial off-the-shelf FPGA add-on card to demonstrate the viability of such approach in low-cost systems. Experiment demonstrated reasonable performance improvement when compared to a typical software-centric implementation; while the number of context switches between FPGA and CPU in both kernel and user mode was significantly reduced, freeing the CPU for other concurrent user tasks.

The extraction, transformation, and loading of event logs from information systems is the first and the most expensive step in process mining. In particular, extracting event logs from popular ERP systems such as SAP poses major challenges, given the size and the structure of the data. Open-source support for ETL is scarce, while commercial process mining vendors maintain connectors to ERP systems supporting ETL of a limited number of business processes in an ad-hoc manner. In this paper, we propose an approach to facilitate event data extraction from SAP ERP systems. In the proposed approach, we store event data in the format of object-centric event logs that efficiently describe executions of business processes supported by ERP systems. To evaluate the feasibility of the proposed approach, we have developed a tool implementing it and conducted case studies with a real-life SAP ERP system.

Within SAP ERP systems, large-scale enterprise environments grapple with financial transaction reconciliation along with compliance monitoring as some of the most intricate and error-prone processes. This research examines automating reconciliation processes augmented with real-time compliance monitoring through the integration of RPA into SAP S/4 HANA. We construct an exception-based RPA framework that processes autonomously accounts receivable, accounts payable and general ledger and bank statement transactions. With enterprise datasets that include payment logs, journals, and audit trails, our system integrates modular RPA workflows to SAP ERP triggers—reducing reconciliation cycle times by 63%, manual interventions by 48%, and compliance flag detections by 72%—with payment logs, journal entries, and audit trails. A domain-specific multi-criteria performance evaluation on reconciliation accuracy, exception handling efficiency, traceability, governance, and alignment agility is introduced alongside the results. The results highlight that transparency, reliability, and scalability of financial operations is enhanced substantially with RPA, proving it provides a forward-looking approach to intelligent ERP automation in compliance-driven SAP environments.

The article presents the basic principles of web services. The comparison with other types of web services is carried out. Analyzed the advantages and disadvantages of different solutions. One of the options for software implementation that allows data transfer between the SAP ERP system and the local systems of the main production units using web services is considered. The result of this work was the implementation and adaptation of a new method of data exchange between systems, the possibility of using received classes and functional modules for the quick creation of following-up web services.

Virtual memory was developed to automate the movement of program code and data between main memory and secondary storage to give the appearance of a single. This technique greatly simplified the programmer’s job, particularly when program code and data exceeded the main memory’s size. In modern operating system, secure file system can protect confidential data from unauthorized access. However, once an authorized process has accessed data from a cryptographic file system, the data can appear as plaintext in the unprotected virtual memory backing store, even after system shutdown. This paper proposes new approach for adding multilevel security capability to virtual memory management. It uses partial swap encryption based on process’s security policy. Volatile encryption keys are chosen randomly, and remain valid only for short time periods. Performance comparison shows the total overhead of proposed method.

Customer Relationship Management (CRM) has become a cornerstone for businesses aiming to build lasting relationships with customers while ensuring operational efficiency. SAP SD (Sales and Distribution) is an essential module within SAP ERP systems that supports companies in managing their sales processes, customer orders, and distribution networks efficiently. This study investigates how the integration of SAP SD enhances CRM practices. By examining its functionalities, such as order management, pricing, and billing, this paper explores how businesses can optimize customer satisfaction and streamline sales operations. The findings emphasize the benefits of using SAP SD for better alignment between sales teams and customers, ultimately fostering customer loyalty and improved revenue growth.

In this paper, we propose a software shared virtual memory (SVM) system for heterogeneous multicore accelerator clusters with explicitly managed memory hierarchies. The target cluster consists of a single manager node and many compute nodes. The manager node contains a generalpurpose processor and larger main memory, and each compute node contains a heterogeneous multicore processor and smaller main memory. These nodes are connected with an interconnection network, such as Gigabit Ethernet. The heterogeneous multicore processor in each compute node consists of a general-purpose processor element (GPE) and multiple accelerator processor elements (APEs). The GPE runs an OS and the multiple APEs are dedicated to compute-intensive workloads. The GPE is typically backed by a deep on-chip cache hierarchy and hardware cache coherence. On the other hand, the APEs have small explicitly-addressed local memory instead of caches. This APE local memory is not coherent with the main memory. Different main and local memory units in the accelerator cluster can be viewed as an explicitly managed memory hierarchy: global memory, node local memory, and APE local memory. Since coherence protocols of previous software SVM proposals cannot effectively handle such a memory hierarchy, we propose a new coherence and consistency protocol, called hierarchical centralized release consistency (HCRC). Our software SVM system is built on top of HCRC and software-managed caches. We evaluate the effectiveness and analyze the performance of our software SVM system on a 32-node heterogeneous multicore cluster (a total of 192 APEs).

Superpage and page coloring are two important practical techniques to improve the performance of Translation Lookaside Buffers (TLBs) and shared Last Level Cache (LLC) respectively. However, there exists a gap between these two techniques in current hardware-architecture design, resulting in the contradiction in adopting these two optimizations simultaneously: a superpage requires hundreds of contiguous (e.g. a power of two) base pages in both virtual and physical memory, which would compulsorily occupy all available page colors (or cache sets), thus making page coloring failed to work. This is because most contemporary architecture adopts the design with cache set indexes placed in the least significant part of block address. In this paper, we propose a lightweight approach named Scattered Superpage to bridge this gap. Scattered Superpage decouples a superpage from the limitation of occupying multiple contiguous physical base pages. A superpage is still contiguous in virtual memory, but it is scattered mapping into multiple physical superpages, and it just occupies specified partial page colors in each physical superpage, thus it allows us to configure page color for each superpage. The huge TLB is slightly modified to store page color configuration for each superpage and to calculate target physical address based on this configuration when doing address translation. The experimental results show that the Scattered Superpage can improve system performance by 20.51% and reduce unfairness by 27.77% in our 4-core simulation system (with multi-program memory-intensive workloads). It achieves this by reducing last level cache miss by 17.05% and reducing TLB miss by 86.02% simultaneously.

Suffix trees for inputs larger than main memory

The diffusion space of data diffusion architectures

In organization contexts, cross-border payments have always been complicated due to exorbitant fees, time delays, and the tangled web of regulations governed by traditional banking systems. This research explores integrating stablecoin transactions into SAP ERP systems to eliminate these gaps and provide instantaneous international transfers at minimal costs. The implementation and testing of a hybrid architecture comprising stablecoin APIs, smart contracts, and custom SAP modules were carried out in multiple geographic and currency contexts. This study uses a design theory methodology to focus on best knowns, measuring performance indicators like transaction latency, savings, system throughput, and compliance. The results confirm consistent improvements of more than 65% in transaction processing time and up to 40% in cost when compared with payment automation methods. In addition, the solution showed strong interoperability with the SAP FI and Treasury modules subject to KYC/AML regulatory controls. This research presents an enterpriselevel adaptable framework for secure stablecoin integration into ERP systems, marking a significant milestone in corporate cross-border payment solutions.

This paper describes a simple distributed mechanism for caching files among a networked collection of workstations. We have implemented it as part of Sprite, a new operating system being implemented at the University of California at Berkeley. A preliminary version of Sprite is currently running on Sun-2 and Sun-3 workstations, which have about 1-2 MIPS processing power and 4-16 Mbytes of main memory. The system is targeted for workstations like these and newer models likely to become available in the near future; we expect the future machines to have at least five to ten times the processing power and main memory of our current machines, as well as small degrees of multiprocessing. We hope that Sprite will be suitable for networks of up to a few hundred of these workstations. Because of economic and environmental factors, most workstations will not have local disks; instead, large fast disks will be concentrated on a few server machines.

This paper addresses new system design issues that will occur when a large quantity of emerging persistent RAM (PRAM) is put on the main memory bus of a platform. First, we anticipate that continued technology advances will enable us to integrate (portions of) the system storage within the PRAM modules on a system board. This change calls for comprehensive re-examination of the system design concepts that assume slow disk and the block I/O concept. Next, we propose Memorage, a system architecture that virtually manages all available physical resources for memory and storage in an integrated manner. Memorage leverages the existing OS virtual memory (VM) manager to improve the performance of memory-intensive workloads and achieve longer lifetime of the main memory.We design and implement a prototype system in the Linux OS to study the effectiveness of Memorage. Obtained results are promising; Memorage is shown to offer additional physical memory capacity to demanding workloads much more efficiently than a conventional VM manager. Under memory pressure, the performance of studied memory-intensive multiprogramming workloads was improved by up to 40.5% with an average of 16.7%. Moreover, Memorage is shown to extend the lifetime of the PRAM main memory by 3.9 or 6.9 times on a system with 8 GB PRAM main memory and a 240 GB or 480 GB PRAM storage.

In the modern chip-multiprocessor system, main memory is a shared resource among multiple concurrently executing threads/applications. The memory scheduling algorithms are developed to resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. This paper presents a new memory scheduling algorithm called Time-Based Least Memory Intensive scheduling (TB-LMI) that addresses system throughput and fairness with the goal of achieving a better throughput and limiting the unfairness. The main idea is to prioritize threads according to their memory contentions every pre-defined period of cycles to improve system throughput and to guarantee fairness. We evaluate TB-LMI on a variety of multi-programmed workloads with different queue sizes of memory controllers and compare its performance to four previously proposed scheduling algorithms. TB-LMI achieves the best system throughput and fairness. On 8-core system, TB-LMI improves system throughput and fairness on average by 4.22% and 11.7% respectively compared to Thread Cluster Memory scheduling (TCM) (previous work providing the best system throughput and fairness). Our newly proposed technique adds negligible area and logic overhead to the Memory Controller compared to the benefits on the system performance.