A 2–20-GHz 10-W High-Efficiency GaN Power Amplifier Using Reactive Matching Technique

A two-stage power amplifier (PA) using GaN HEMTs is presented with a high power added efficiency (PAE) and good linearity. This PA employs a structure of a class-C PA driving a class-AB PA to obtain a high PAE while maintaining the linearity. Source-pull and load-pull techniques were implemented to achieve optimum output impedance and inter-stage matching condition to compromise the PAE and the linearity of the overall circuit. When producing a two-tone carrier-to-intermodulation (C/I) ratio of 30 dB with the 1 MHz space, the two-stage PA exhibits a maximum PAE of 47% with an output power of 3 W at 3.7 GHz. The PA provides a maximum output power of 7 W with the gain of 15.8 dB.

Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (f max > 340 GHz) with the high voltage capability (V DD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.

In this article, we propose a broadband fully integrated power amplifier (PA) using a waveform shaping harmonic matching network. A comprehensive theory is developed for the proposed multi-resonance harmonic matching network to derive design criteria for achieving wide bandwidth, low insertion loss, and optimum load impedances in the second- and third-harmonic frequency bands. Furthermore, it is shown that this network can be realized using a lower total inductance compared to a standard bandpass network which is an important feature in reducing chip area and fabrication cost. A fully integrated PA prototype is implemented using a 250-nm GaN-on-SiC process with 28-V supply. The PA provides 33.9–36.1dBm output power (at 2–3dB gain compression), 42–51% drain efficiency (DE), 38–48% power-added efficiency (PAE), and 10–12.2dB power gain, across 4.0–6.0GHz. The output-power 1-dB bandwidth is 3.6–5.6GHz (44.5%). For a 64-QAM signal with 8dB peak-to-average power ratio (PAPR) at 5.0GHz, the PA can provide 30.2dBm average output power and 32% average PAE with RMS error vector magnitude (EVM) of −34.0/−32.4/−28.4dB (2.0/2.4/3.8%) for 50/100/200MHz modulation bandwidth, without using digital predistortion (DPD). The maximum average output power and average PAE, under the linearity constraint EVM <−28dB, are respectively 32.1/32.0/30.2dBm and 39/38/32%, for modulation bandwidth of 50/100/200 MHz.

In this paper, we propose a systematic approach to designing a highly efficient two-stage power amplifier (PA) with improved linearity. Investigation into the sources of nonlinearity in gallium nitride (GaN) high electron mobility transistors (HEMT) has been essential prior to the development of the two-stage PA design with improved linearity. A prototype was designed and fabricated using 45W and 6W packaged CREE transistors as the main and driver stages respectively. A peak efficiency of about 70% was obtained, using a continuous wave stimulus, over a bandwidth of 200MHz. When driven with a 20MHz WCDMA signal, at 800MHz, an adjacent channel leakage power ratio (ACLR) of 46dBc and an error vector magnitude (EVM) of about 1.5% were recorded at a peak output power of 39dBm without the use of digital pre-distortion (DPD). These results represent an improvement of about 10dB in ACLR and 2% in EVM for the two-stage PA using nonlinear driver as compare to those obtained using a linear driver.

A new monolithic microwave integrated circuit power amplifier for 802.11b/g wireless local area network (WLAN) has been implemented using the load modulation concept of a Doherty amplifier. The λ/4 transmission line for the load modulation circuit of the carrier amplifier is replaced by a lumped element based π-network, which dual functions as an output matching network, simultaneously. This amplifier shows that error vector magnitude is about 4.6% and power added efficiency (PAE) about 31.8% at Pout of 19 dBm for a 802.11g 64QAM signal. PAE of the power amplifier is about 49.6%, and adjacent channel leakage ratio below 37.2dBc at 11 MHz offset at Pout of 23 dBm for the 802.11b complementary code keying signal.

: A key component of microwave telecommunication systems is the power amplifier (PA). The design parameters of a communication system, such as link performance, power budget, and thermal design are typically driven by the power amplifier's linearity, output power, and efficiency. These design parameters of PA are the key to ensuring an efficient system because the PA is the most power-consuming circuit in the communication system. In an effort to have students involved in this research area, the International Microwave Symposium (IMS) sponsored by IEEE Microwave Theory and Technique Society (MTT-S) has introduced a High Efficiency Power Amplifier Design Competition. In this report, we present a 2.8-GHz, 5-W, highly efficient PA based on a wide bandgap gallium nitride (GaN) high electron mobility transistor (HEMT) device (CGH 40010f from CREE). The PA design was presented at the 2010 IMS Student Design Competition and achieved the competition goal of output power greater than 5 W with a measured power added efficiency (PAE) of 61% at 2.8 GHz.

In this paper, the high potential of varactor-based dynamic load modulation (DLM) techniques for wideband cellular applications is demonstrated. A systematic design procedure is proposed to ensure high-efficiency wideband performance. It incorporates harmonically tuned power amplifier (PA) concepts and tunable matching techniques in an integrated design. A DLM transmitter at 2.65 GHz with a peak output power of 6 W is designed using the proposed procedure. In order to investigate the wideband performance of the implemented demonstrator, WCDMA signals with scaled bandwidths are employed. The signal peak-to-average ratio is 7 dB and the same for all the experiments. For the 38.4-MHz signal, which has a corresponding channel bandwidth of > 40 MHz, an average power added-efficiency (PAE) of 44%, normalized mean square error (NMSE) of -35 dB, and adjacent channel leakage ratio (ACLR) of -43 dBc are measured.

Recent advances in both high power millimeter wave (mmW) Gallium Nitride (GaN) technology and high-speed System on Chip (SoC) modem technology has enabled the development, fabrication, and field testing of a high speed, long range wireless datalink with fiber equivalent speed. The link exhibited nearly an 80 Gbps bi-directional data rate (40 Gbps in each direction) over a range of 16km. This was accomplished by using a combination of frequency and polarization multiplexing to combine a total of eight ∼10 Gbps modem channels on the lower (71–76 GHz) and upper (81–86 GHz) E-band channels. Each modem channel was separately up-converted and amplified with a Gallium Nitride (GaN) power amplifier. Frequency multiplexing was accomplished at E-band (post-amplification) to maintain high Power Added Efficiency (PAE) in the power amplifiers.

This paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.

This paper presents a new class of power amplifier (PA) - Class-iF- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> - resolving the highly nonlinear double inflection characteristics in the conventional Class-F- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> PA. It is illustrated that, by properly terminating the second harmonic source impedance Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2S</inf> from conventional short-circuit to open-circuit, the double inflection nonlinear gain profile can be mitigated in the proposed Class-iF- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> PA, wherein the same saturation output power is achieved with less gain compression without drain efficiency trade-off. The idea was validated with source/load-pull and a broadband prototype operating from 2.0 to 2.6 GHz was designed using a commercial 10-W Gallium Nitride (GaN) transistor. Under continuous wave (CW) signal test, the proposed Class-iF- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> PA can achieve 40.1-40.8-dBm output power, 71.2%-77.3% drain efficiency (DE) and 67.4%-74.1 % power added efficiency (PAE) at 3-dB gain compression level over 2.0-2.6 GHz.

In this paper, we present a high-efficiency S-band gallium nitride (GaN) power amplifier (PA). This amplifier is fabricated based on a self-developed GaN high-electron-mobility transistor (HEMT) with 10 mm gate width on SiC substrate. Harmonic manipulation circuits are presented in the amplifier. The matching networks consist of microstrip lines and discrete components. Open-circuited stub lines in both input and output are used to tune the 2nd harmonic wave and match the GaN HEMT to the highest efficiency condition. The developed amplifier delivers an output power of 48.5 dBm (∼70 W) with a power-added efficiency (PAE) of 72.2% at 2 GHz in pulse condition. When operating at 1.8–2.2 GHz (20% relative bandwidth), the amplifier provides an output power higher than 48 dBm (∼ 65 W), with a PAE over 70% and a power gain above 15 dB. When operating in continuous-wave (CW) operating conditions, the amplifier gives an output power over 46 dBm (40 W) with PAE beyond 60% over the whole operation frequency range.

This paper presents a novel design approach of CMOS power amplifier (PA) using 50Ω matched coplanar waveguide component which improves the power efficiency for K-band applications. This new technique of designing PA also enhances the data transmission rate and achieves saturated output power in the desired frequency band. A two stage CMOS PA is designed in which coplanar waveguide line is used in order to provide broadband multi-section matching networks which could improve bandwidth, output power, power gain and power added efficiency (PAE). A two-stage CMOS PA design is simulated using predictive technology model (PTM) 65nm CMOS process in ADS.v.12. A simulation result of PA achieves a reflection parameter of −43.06dB at 23GHz with forward gain of 15.6dB over the frequency band of 20.5–24.5GHz. The best achievement of design is to achieve PAE of 58% using the concept of coplanar waveguide.

A generalized dual-input digital predistortion (DPD) methodology for supply-modulated (SM) power amplifiers (PAs) is proposed. Contrary to classical approaches, the SM and the radio frequency (RF) signals are treated as separate digital inputs to be jointly predistorted. A multi-objective optimization (MOO) strategy allows to explore the inherent PA performance tradeoffs to jointly optimize the DPD coefficients for improved power-added efficiency (PAE) and higher RF output power, yet guaranteeing a prescribed linearity performance. To avoid dealing with an unbearably high number of experimental acquisitions, MOO is here made feasible by fast simulation of an empirical surrogate model of the PA, which is progressively refined from a reduced set of iterative acquisitions. The proposed technique enables the adoption of a dynamic supply shaping function, and it automatically accounts for the signals’ statistics. Eventually, the method outperforms classical SM approaches, yet using a DPD of the same order, as demonstrated by the experimental results on a gallium nitride (GaN) SM PA operating at 3.5 GHz in the presence of orthogonal-frequency-division-multiplexing (OFDM)-like high-peak-to-average power ratio (PAPR) modulated signals with 10- and 20-MHz bandwidths (BWs).

This work presents radio-frequency-microelectromechanical-system (RF-MEMS)-based tunable matching networks for a multi-band gallium nitride (GaN) power amplifer (PA) application. In the frequency range from 3.5–8.5 GHz return losses of 5–10 dB were measured for the input network, matching impedances close to the border of the Smith chart. For the output matching network return losses of 10–20 dB and insertion losses of 1.3–2 dB were measured. The matching networks can tune the PA to four different operating frequencies, as well as changing the transistor's mode of operation from maximum delivered-output-power to maximum power-added-efficiency (PAE), while keeping the operating frequency constant. Furthermore, different single pole double throw (SPDT)-switches are designed and characterized, to be used in frequency-agile transmit/receive-modules (T/R modules).

This paper presents the first linear bulk CMOS power amplifier (PA) targeting low-power fifth-generation (5G) mobile user equipment integrated phased array transceivers. The output stage of the PA is first optimized for power-added efficiency (PAE) at a desired error vector magnitude (EVM) and range given a challenging 5G uplink use case scenario. Then, inductive source degeneration in the optimized output stage is shown to enable its embedding into a two-stage transformer-coupled PA; by broadening interstage impedance matching bandwidth and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured $P_{\text {out}}$ /PAE at −25 dBc EVM for a 250 MHz-wide 64-quadrature amplitude modulation orthogonal frequency division multiplexing signal with 9.6 dB peak-to-average power ratio. The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6 dB back-off from saturation. To the best of the authors’ knowledge, these are the highest measured PAE values among published ${K}$ - and Ka -band CMOS PAs.