Class-iF−1: Linearity Enhanced High Efficiency Power Amplifier

This article presents the analysis and design of a three-stage load modulated power amplifier (PA), in which three amplifiers, each with different biasing, are connected to a four-port coupler. It is illustrated that, by properly configuring current relationships between the three amplifiers, this new load modulated PA can provide flexible output power back-off (OBO) and achieve high efficiency within a large OBO range. A detailed theoretical analysis and design methodology are given. In this architecture, the OBO level can be adjusted by simply setting bias conditions of the relevant amplifiers that correspond to the current relationships. Therefore, after circuit fabrication, the OBO range can still be reconfigured without redesigning the circuit. To validate the proposed approach, a prototype operating at 3.45 GHz is demonstrated and implemented with gallium nitride (GaN) transistors. The measured saturated output power reaches 45 dBm with 70.1% drain efficiency. At 6-/8-/10-dB OBO, the fabricated PA can provide up to 62.1%/53.8%/47.3% drain efficiency, respectively. When driven by a 60-MHz 9-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal, the PA provides 34-dBm average output power with 44.3% average efficiency. Moreover, measurement results prove that the PA can offer efficiency enhancement when the OBO is reconfigured to 8 or 12 dB after fabrication.

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of <TEX>$0.4-{\mu}m$</TEX> and <TEX>$0.25-{\mu}m$</TEX> in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a <TEX>$0.25-{\mu}m$</TEX> transistor. The possibility of using a <TEX>$0.4-{\mu}m$</TEX> transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of <TEX>$0.4-{\mu}m$</TEX> transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the <TEX>$0.25-{\mu}m$</TEX> transistor.

This paper presents a high efficiency class-E power amplifier (PA) suitable for wireless transmitters operating at 2 GHz. Compact impedance transformation network is designed, using micro-strip transmission lines, so that it simultaneously achieves fundamental load transformation and harmonic impedance control using only two open-circuit stubs (2fo, 3fo). The dimensions of the network’s elements were determined in order to concurrently attain a high harmonic suppression, minimum loss and high power added efficiency. The measurement results of the PA prototype, which is designed using a 10 W Gallium Nitride (GaN) HEMT transistor, showed state-of-the-art drain and power added efficiency (PAE). The achieved PAE, power gain and output power, when the drain is biased at 50V, were equal to 74%, 12.6 dB and 11.4W respectively. In addition, a second and third harmonic suppression in excess of −40 dBc and −75 dBc, respectively, is achieved without extra circuit tuning or additional filtering.

In this paper, we present a monolithic microwave-integrated circuit (MMIC) asymmetric Doherty power amplifier (ADPA) using 0.25[Formula: see text][Formula: see text]m gallium-nitride (GaN) process with a compact chip size of 2.9 mm × 1.9 mm in wireless transmitters. Two different power amplifiers are adopted to solve the contradiction between the output power and efficiency of the conventional Doherty power amplifier (CDPA). In addition, phase compensation and low Q impedance inverting network (IIN) technology are used in the input and output matching networks, respectively, to expand the bandwidth of the entire ADPA. The post-layout simulation results show that the designed ADPA has a saturation output power 42.5 dBm with 800 MHz bandwidth from 6.6 to 7.4 GHz. The ADPA demonstrates 36.8–41.8% power-added efficiency (PAE), whereas 44–54% drain efficiency (DE) is achieved at saturation power.

In this paper, a 3.2–3.6 GHz two-stage Doherty power amplifier (PA) module is proposed for fifth-generation (5G) massive multiple-input multiple-output (MIMO) base stations. A detailed design method and procedure for a compact and low-loss combiner suitable for the Doherty PA module are introduced. Based on the proposed combiner, a Doherty PA module is implemented using gallium nitride (GaN) transistors and surface-mounted devices (SMDs) with a packaged size of 8 × 8 mm2. The proposed two-stage Doherty PA module achieves a 3 dB small-signal bandwidth of 3.1–3.9 GHz and a peak gain of 31.7 dB. From 3.2 to 3.6 GHz, the saturated output power is 40.4–41.1 dBm. Moreover, the measured saturated drain efficiency (DE) and 8 dB power back-off (PBO) DE reach 51–56.6% and 45.5–48.6%, respectively.

: A key component of microwave telecommunication systems is the power amplifier (PA). The design parameters of a communication system, such as link performance, power budget, and thermal design are typically driven by the power amplifier's linearity, output power, and efficiency. These design parameters of PA are the key to ensuring an efficient system because the PA is the most power-consuming circuit in the communication system. In an effort to have students involved in this research area, the International Microwave Symposium (IMS) sponsored by IEEE Microwave Theory and Technique Society (MTT-S) has introduced a High Efficiency Power Amplifier Design Competition. In this report, we present a 2.8-GHz, 5-W, highly efficient PA based on a wide bandgap gallium nitride (GaN) high electron mobility transistor (HEMT) device (CGH 40010f from CREE). The PA design was presented at the 2010 IMS Student Design Competition and achieved the competition goal of output power greater than 5 W with a measured power added efficiency (PAE) of 61% at 2.8 GHz.

The long-term memory effects of gallium nitride (GaN) transistors have prevented its use in situations where the modulated envelope signal has a wide amplitude variation over time, such as in time division duplex systems. These long-term memory effects are generally attributed to electron trapping in GaN high electron-mobility transistors (HEMT), which have shown to be very difficult to compensate, especially in cellular base station transmitters known to be subjected to highly restrictive linearity specifications. On top of the electron trapping effects, we show that thermal effects can also induce long-term memory behaviors, which should also be accounted for when linearizing these devices. Because the conventional behavioral modeling approach has been incapable to compensate these long-term memory effects on GaN HEMT-based power amplifiers (PAs), we started by investigating the physical mechanisms responsible for these semiconductor impairments in GaN devices. This physics-based knowledge was then used to design new predistorter models that could effectively compensate those PAs subjected to GaN trapping and thermal effects. In this paper, we describe the new predistortion models for PA linearization, as well as the characterization methods used to determine their parameters. To validate the linearization effectiveness of the proposed model, several high power GaN-based PAs are tested with multicarrier GSM signals, and their linearization results are compared against other state-of-the-art models, evidencing a clear and significant improvement. In fact, to the authors’ knowledge, the proposed approach is the first one to reduce the PA distortion effects due to GaN long-term memory effects to such low levels, allowing a comfortable compliance with the imposed linearity masks.

In order to meet the requirements of high efficiency and broadband for the wireless communication system, a high efficiency and broadband gallium nitride power amplifier (PA) is designed and verified. Using the step-matching structure, its bandwidth has been improved. Furthermore, its input matching network is constructed by connecting several microband lines serially to reduce the matching Q value. Meanwhile, the harmonic control network is designed as the output matching network, which is built by a quarter-wave (λ/4) line open circuit and short circuit microwave lines in parallel. Thus, its drain efficiency (DE)can be improved. This design is simulated and tested at 2.2–3 GHz with the gallium nitride (GaN) process. After measuring, it attains an output power (Pout) of 39.5–41.5 dBm, Gain of 10.5–12.5 dB, DE of 65.1%–78.3% with power added efficiency (PAE) of 64.8%–76.2%.

In this paper, we present a high-efficiency S-band gallium nitride (GaN) power amplifier (PA). This amplifier is fabricated based on a self-developed GaN high-electron-mobility transistor (HEMT) with 10 mm gate width on SiC substrate. Harmonic manipulation circuits are presented in the amplifier. The matching networks consist of microstrip lines and discrete components. Open-circuited stub lines in both input and output are used to tune the 2nd harmonic wave and match the GaN HEMT to the highest efficiency condition. The developed amplifier delivers an output power of 48.5 dBm (∼70 W) with a power-added efficiency (PAE) of 72.2% at 2 GHz in pulse condition. When operating at 1.8–2.2 GHz (20% relative bandwidth), the amplifier provides an output power higher than 48 dBm (∼ 65 W), with a PAE over 70% and a power gain above 15 dB. When operating in continuous-wave (CW) operating conditions, the amplifier gives an output power over 46 dBm (40 W) with PAE beyond 60% over the whole operation frequency range.

A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.

본 논문에서는 접지 결함 구조(Defected Ground Structure: DGS)를 이용하여 기지국용 고효율 E급 전력 증폭기의 성능을 유지하면서 크기를 소형화 할 수 있는 방안을 제안하였다. E급 전력 증폭기에서 요구되는 고조파 임피던스는 아령형 DGS와 나선형 DGS를 사용함으로써 만족시켜 주었다. 제안하는 유사 E급 전력 증폭기의 DGS 부하 회로는 가장 큰 고조파 성분인 2차 고조파 대역에서 개방, 나머지 고차 고조파 임피던스는 단락에 가까운 고조파 임피던스를 갖는다. 제안하는 구조를 통하여 제작된 전력 증폭기는 출력 전력이 43.1 dBm, 포화전력 이득이 12.7 dB일 때 70.2 %의 전력 부가 효율(Power Added Efficiency: PAE)을 가지며, 이는 비교 대상인 E급 증폭기와 거의 유사한 값이다. 회로 크기의 관점에서 보면 각각의 고조파 성분 정합을 위해 여러 개의 스터브가 장착되어 있는 비교 대상인 E급 증폭기에 비해 전체 크기를 50 %로 소형화시킬 수 있었다. In this work, a reduced size 20W quasi class-E Power Amplifier(PA) with defected ground structure load-network is presented for WCDMA base station application. Harmonic impedances required for the class E operation are satisfied by applying the dumbbell and the asymmetric spiral DGS. Open impedance for 2nd harmonic frequency which has the highest power and nearly short impedances for other higher order harmonics are provided by the proposed DGS load-network. The maximum Power Added Efficiency(PAE) of 70.2 % at the output power of 43.1 dBm with the saturated power gain of 12.7 dB is achieved by the proposed quasi class-E PA, which is comparable to the performance of the reference class-E PA. Total size of the proposed class-E PA is only <TEX>$50{\times}50\;mm^2$</TEX> and much smaller than the conventional class-E PA that is loaded with a number of open stubs.

This paper presents a CMOS inverter-like Class-D/E switching power amplifier (PA). The proposed amplifier operates in-between Class-E and Class-DE PAs. For proper operation of a Class-E PA, an RF choke (RFC) with large inductance value and high self-resonant frequency is necessary. A Class-DE PA does not require an RFC but requires a dead-time between OFF-ON transitions of the two switches. The proposed PA uses two complementary switches and requires neither an RFC nor a dead-time for its operation. For the same supply voltage and the load resistance, the voltage stress on each switching device in the proposed PA is less than the voltage stress in a Class-E PA. Design and simulation results of a prototype PA at 2.45 GHz with +20 dBm output power are presented.

Design and implementation of a high-efficiency concurrent dual-band power amplifier

In order to meet the increasing demands of wireless communication for ISM bands, a 433 MHz transmitter RF front-end is designed using a 55 nm low-power CMOS technology. The circuits consist of an active mixer, a driver amplifier and a class-E power amplifier (PA). A double-balanced Gilbert active mixer is designed to realize binary phase-shift keying (BPSK) modulation. The driver is used to preamplify the modulated RF signals. The class-E PA adopts a parallel four-branch cascode structure to control the output power level. The load network of the PA is implemented through an off-chip circuit, in which a finite DC-feed inductance load network is selected to reduce the power loss. The mixer and driver are designed with a 1.2 V supply voltage, while the PA is operated at a 1.8 V supply voltage. The area of the chip is 0.206 mm × 0.089 mm, and the measured results show that it achieves a maximum output power of 2.7 dBm, with a total power consumption of 6.72 mW. At a drain efficiency (DE) of 34.5%, an S22 less than −10 dB over the frequency ranges from 393.79 MHz to 455.70 MHz can be measured for the PA. With 192 kbps BPSK data modulated at 433 MHz, the measured EVM is about 0.83% rms.

The high-power operation of a modular and compact power amplifier (PA) is demonstrated using gallium nitride (GaN) transistors and power-combining networks implemented on an aluminum nitride (AlN) substrate. The power-combining network, tuned for X-Band operation, includes matching circuits and Wilkinson power dividers (WPDs) with tantalum nitride (TaN) thin-film resistors. PA efficiency is increased by minimizing network thermal loss with the AlN substrate, which is an excellent thermal conductor. All system components were mounted on a metal carrier, and were interconnected through gold wire bonds. Large-signal measurements showed power added efficiency (PAE) of 44 % and a peak output power of 6.5 W at 9.5 GHz with a 3 dB fractional bandwidth of 14 %.