A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Analog-mixed signal (AMS) circuits are widely used in various mission-critical applications necessitating their formal verification prior to implementation. We consider modeling two AMS circuits as hybrid automata, particularly a charge pump phase-locked loop (CP-PLL) and a full-wave rectifier (FWR). We present executable models for the benchmarks in SpaceEx format, perform reachability analysis, and demonstrate their automatic conversion to MathWorks Simulink/Stateflow (SLSF) format using the HyST tool. Moreover, as a next step towards implementation, we present the VHDL-AMS description of a circuit based on the verified model.

We present ABCD-NL, a technique that approximates non-linear analog circuits using purely Boolean models, to high accuracy. Given an analog/mixed-signal (AMS) system (e.g., a SPICE netlist), ABCD-NL produces a Boolean circuit representation (e.g., an And Inverter Graph, Finite State Machine, or Binary Decision Diagram) that captures the I/O behaviour of the given system, to near SPICE-level accuracy, without making any apriori simplifications. The Boolean models produced by ABCD-NL can be used for high-speed simulation and formal verification of AMS designs, by leveraging existing tools developed for Boolean/hybrid systems analysis (e.g., ABC [1]). We apply ABCD-NL to a number of SPICE-level AMS circuits, including data converters, charge pumps, comparators, non-linear signaling/communications sub-systems, etc. Also, we formally verify the throughput of an AMS signaling system - modelled in SPICE using 22nm BSIM4 transistors, Booleanized with high accuracy using ABCD-NL, and property-checked using ABC.

Among different types of regression methods to model Analog/Mixed-Signal (AMS) circuits, the Artificial Neural Network (ANN) is a promising candidate due to its reasonable accuracy and fast evaluation. However, for complex AMS circuits with wide specification ranges, creating an ANN model requires a large training dataset. To reduce the required training dataset’s volume, we have proposed a circuit-connectivity-inspired ANN (CCI-NN), including multiple sub-ANNs linked according to the actual circuit connections. For validation, we have employed CCI-NN to model a three-stage amplifier and a current-steering digital-to-analog converter. For a certain modeling accuracy, the training dataset requirement is reduced by 3.5x-7.6x.

The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

The authors explore the tradeoff between the area of a programmable gate array (PGA) and the functionality of its logic block. A set of industrial circuits is implemented as PGAs using tools for technology mapping, placement, and routing. A simple model allows the exploration of a range of programming technologies and accounts for the area required by wiring. Experiments indicate that for combinational logic blocks implemented using lookup tables, the best number of inputs to use is between three and four, and that a D flip-flop should always be included in the logic block. These results are independent of the programming technology

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This article describes our novel masked dual-rail pre-charged memory approach, called “intra-masking dual-rail memory (IMDRM) on LUT”, and its implementation on FPGA for Side-Channel Attack-resistant (SCA-resistant) AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and parts of dual-rail memory with unsafe buses (buses that are not masked) are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. Inputs and outputs of all LUTs are masked, and so can be considered safe signals. Several LUTs can be combined to create a safe SBox. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced SCA-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

Neutron radiation environment in near space is analyzed by Space Radiation 7.0 toolkit. It is found that neutron flux decreases by several orders as altitude increases, low-energy neutron flux increases sharply at solar maximum condition, neutron flux increases constantly as latitude ascends. The inner reasons are further investigated. Based on the results, a prediction technique of atmospheric-neutron induced Real-Time Soft Error Rate (RTSER) using Monte-Carlo method is proposed. Taking Field Programmable Gate Array (FPGA), critical Integrated Circuit (IC) used in avionics system, as an example, the RTSERs of Single Event Upset (SEU) sensitive modules (including Configurable Memory (CM), Block Random Access Memory (BRAM) and user Flip-Flops (FF)) and Single Event Functional Interrupt (SEFI) sensitive modules (including Power-On-Reset (POR), SelectMAP <i>etc</i>.) are predicted. The results show that SEUs in CM accounted for 77% of the total SEU rate in the FPGA. Both POR and SelectMAP SEFIs accounted for 36% of the total SEFI rate respectively. According to the failure levels of flight system in RTCA DO-254, the FPGA can not be employed in key positions of avionics.

The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead.

Static random-access-memory-based field-programmable gate array devices are an attractive option for onboard data processing in space systems due to higher computational capabilities and a lower power envelope than traditional processing devices. However, field-programmable gate arrays present unique reliability verification challenges because single-event upsets can trigger both data errors and configuration memory errors, which may cause deviations from the expected system functionality. To evaluate system reliability, traditional fault-injection testing uses numerous test vectors to observe the effects induced by a change of a single configuration memory bit at a time. This single-bit fault-injection methodology provides high fault coverage and testing repeatability, but it requires a long fault-injection time due to the large number of test vectors required to verify the entire design’s functionality. Long injection times are further exacerbated as configuration memory size and design complexity increase. To shorten injection time, a Simple, Portable Fault Injector platform is proposed for field-programmable gate arrays used in tandem with a novel multibit fault-injection methodology that modifies multiple configuration memory bits, referred to as a batch, during each test. The proposed methodology is optimized to efficiently detect the faulty bits within a batch, adaptively select the optimal batch size, and optimize the fault-injection sequence based on the design’s placement. Using relevant case studies, Simple, Portable Fault Injector for field-programmable gate arrays augmented with multibit fault-injection methodology reveals up to 50 times the speedup in fault-injection time.

In this chapter we present an experimental methodology to study the Single Event Effects (SEE) in Field Programmable Gate Arrays (FPGAs) by using heavy ion beam irradiation. We present also some results obtained at a Van Der Graaff Tandem accelerator facility. Test methodology is based on the implementation of four Shift-Registers (SRs), two of them by using Triple-Modular-Redundant (TMR) technique. The SRs functionality is continuously checked during irradiation and errors are immediately and automatically logged and timestamped by the control system. Irradiation experiments have been performed on commercial FPGAs manufactured by Altera. These devices are based on static RAM configuration memory. No Single Event Upset (SEU) was detected in the shift registers upon irradiation. Instead, the predominant effect of heavy ion irradiation was the Single Event Functional Interrupt (SEFI). SEFIs are likely induced by SEUs in the configuration memory. No destructive latch-up has been observed. During irradiation, supply current has been observed to increase almost linearly with ion fluence, probably due to progressive SEU-induced driver contentions. The configuration memory cross section has been calculated.Key wordsFPGAirradiationCOTSSEUSEFI

Objectives. Programmable logic integrated circuits of the field programmable gate array (FPGA) type based on static configuration memory are widely used in the electronics of onboard spacecraft systems. Under the influence of space radiation, errors may occur in the FPGA configuration memory. The main methods of protection against such errors involve various options for reservation triggers, as well as the use of error-correcting codes in special error detection and correction circuits. The purpose of the present work is to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.Methods. The paper analyses various methods for scrubbing FPGA configuration memory, which are used to correct errors caused by the action of space radiation. It is proposed to increase the efficiency of internal scrubbing of the FPGA configuration memory using codes that correct both single- and double-adjacent SEC-DED-DAEC errors. In this case, the need to perform external scrubbing of the configuration memory is reduced by overwriting it with a reference configuration from non-volatile radiation-resistant memory; in this way, FPGA downtime caused by the external scrubbing procedure is reduced. Due to the known SEC-DED-DAEC codes having a non-zero probability of erroneous detection and subsequent erroneous correction of a double non-adjacent error, as well as various redundancy and implementation complexities, a study was made of the most efficient code for internal scrubbing.Results. The results showed that the Datta, Neale and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.Conclusions. The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.

SRAM-based FPGA designs are extremely susceptible to single event upset (SEUs). Since the configuration memory defines which is the circuit an SRAM-based field programmable gate array (FPGA) implements, any change induced by SEUs in the configuration memory may modify drastically the implemented circuit. When such devices are used in safety-critical applications, fault tolerant techniques are needed able to mitigate the effects of SEUs in FPGA's configuration memory. In this paper we present a reliability-oriented place and route algorithm that is able to mitigate the effects of the considered upsets.

This paper presents a novel strategy to improve the accuracy of macromodel-based approaches for fast Signal Integrity assessment for highly integrated Radio Frequency (RF) and Analog-Mixed-Signal (AMS) Systems on Chip (SoC). Specifically, we focus on small-signal representations of non-linear circuit blocks (CB) at prescribed DC operation points, which are approximated with low-order linearized macromodels to speed up the complex transient simulations required by common Signal-Integrity (SI) and Power Integrity (PI) verifications. In this paper, we propose a simple yet effective DC point correction strategy of the low-order macromodels, which enables their safe use in complete verification testbenches by ensuring exact biasing conditions for all circuit blocks. The numerical results show the effectiveness of the proposed model enhancement methodology, both in terms of accuracy and simulation time, when applied to several test cases of practical relevance for AMS and RF simulations.