A boundary scan architecture using multiple-valued logic

A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed. >

In this paper we present a new BIST test pattern generator architecture and a methodology to program this architecture to generate tests for any given inter-chip interconnect circuitry via IEEE 1149.1 boundary-scan architecture. The test architecture uses two test pattern generators, a C-TPG that generates test patterns for the control cells in the boundary scan chain and a D-TPG that generates rest patterns for the data cells. The other main component of the test architecture is a lookup table which is programmed to select, for each boundary scan cell, a specific C-TPG or D-TPG stage whose content is shifted into that cell. This test architecture provides a complete BIST solution for interconnect testing. The proposed BIST TPG design procedure uses the notions of incompatibility and conditional incompatibility and generates TPG designs that (i) guarantee that no circuit damage can occur due to multi-driver conflicts, (ii) guarantee the detection of all interconnect faults, (iii) have low area overhead, and (iv) have low test length. The proposed procedure is used to obtain TPG designs that require significantly less test time and area than other TPG designs, for eight interconnect circuits extracted from industrial boards.

A new mixed-mode boundary scan architecture is developed. The digital part of this architecture complies with the IEEE Std 1149.1. For the analogue part, we propose a new boundary scan cell design and define 4 analogue test instructions. The control signals for each instruction are also described.

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes. >

The design, implementation, and testing of a gallium arsenide phasing and fanout buffer are described. The integrated circuit provides a method for adjusting the phasing of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described buffer can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fanout buffer and provides 12 in-phase outputs. The buffer is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components. >

System-in-Package (SiP) is where multiple dice, along with passive components, are mounted onto a common substrate. For the purposes of testing, the substrate can be viewed as simply a printed circuit board. If viewed as such, there are two IEEE standards that can be used very effectively to provide testing of SiPs, (1) 1149.1 A Test Access Port and Boundary Scan Architecture, and (2) 1149.4 A Standard Mixed Signal Test Bus.

IEEE 1149.7 (Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary Scan Architecture) is a superset of the 1149.1 JTAG interface, which, as previously discussed, has been in use since 1990. The IEEE 1149.7 standard (also known in the past as cJTAG or Compact JTAG, and later as aJTAG or Advanced JTAG due to copyright issues with the name CJTAG) was developed to address some of the known limitations of 1149.1 performance and extend its ­capabilities by creating a complementary standard that addresses the changes in the integrated circuit technology and topology. Originally defined as part the MIPI Test and Bdebug Working Group, 1149.7 defines a hierarchy of new, but JTAG compatible capabilities. With increasing levels of complexity, it replaces the JTAG TAP FSM with alternate TAP.7 architectures to implement additional functionality and maximize debug performance. Like other JTAG extension, a key concern is to maintain backward compatibility with IEEE 1149.1 infrastructure, semiconductor IP, software IP, and existing debug and test tools.

Multiple negative-differential-resistance switches based on an InGaP/GaAs/InGaAs step-compositional-emitter bipolar transistor for multiple-valued logic application

A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.

Due to advances in power transistor technologies, higher switching frequencies and steeper switching slopes are used in motor inverters to achieve higher efficiency and power density. However, this leads to increased electromagnetic interference (EMI). Conventional passive filter topologies can use a considerable amount of space and contain heavy components, reducing overall power density. To minimize volume and weight of passive filters, active EMI filters can be used. In this work, a novel EMI cancellation method for pulsewidth modulation controlled three-phase motor inverters is presented in a feasibility study. This method injects a cancellation signal by applying a filter to the digital transistor control signals of the motor inverter. By slightly delaying the control signals before they reach the transistor gates, the time required to synthesize and inject the cancellation signal can be compensated. The digital filter parameters are adapted continuously based on the measured noise signal to achieve maximum filter performance. First, the new method is described in general. After that, the applicability to power electronics is discussed. For demonstration, the system is applied to a motor inverter with GaN transistors to reduce the conducted common mode EMI at the input side of the inverter. The results are shown and discussed for different operation modes.

The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. A similar standard for analog circuits is yet to be set up. In this paper we propose a new analog boundary scan architecture which is similar to the IEEE Std. 1149.1. The basic analog boundary scan cell, the defined instructions, the associated operations, and the control circuitry are described. The advantages of this architecture include: (1) Signal at various test points can be sampled simultaneously, (2) test stimuli can be injected to various test points simultaneously, and (3) test stimuli loading and test response outputting can be done simultaneously.

As the technology is shrinking and the working frequency is going into the multi Gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically, signal integrity loss issues are becoming more important, and detection and diagnosis of these losses are becoming a great challenge. In this paper, an enhanced boundary scan architecture, with slight modification in the boundary scan cells, is proposed to test signal integrity in SoC interconnects. Our extended JTAG architecture: 1) minimizes scan-in operation by using modified boundary scan cells in pattern generation; and 2) incorporates the integrity loss information within the modified observation cells. To fully comply with the JTAG standard, we propose two new instructions, one for pattern generation and the other for scanning out the captured signal integrity information.

A vertically integrated test methodology has been developed for ASIC testing based on the IEEE 1149.1 Standard Test Interface. A common interface is used to test at the wafer, packaged-chip and board/system levels. The boundary scan JTAG interface is combined with an internal full scan based test technique to provide a uniform test procedure at all stages of testing. At the prototype debug phase, the test circuitry is configured to test for design and process faults. At the manufacturing stage, it allows for efficient wafer sorting and packaged chip testing. At the board/system level, the same test set used at the wafer and package levels can be employed for incoming-inspection of parts and in-circuit-testing. In addition to basic scan testing, the protocol can perform AC/delay-fault testing. For embedded megacell and RAM module testing it is configured to control and operate an independent BIST scheme inside the ASIC device to achieve at-speed testing. This test methodology has been implemented on practical ASIC parts. The area overhead for the boundary scan architecture is on the order of a few percent for 30-50 K gate designs, and depending on the type of implementation, performance overhead varies from minimal to no penalty at the I/O cells.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The number of chip pins is limited due to the cost and reliability issues of sophisticated packages, and it is predicted that the chip pin count will be overstretched to satisfy the requirements of both power delivery and memory access. The gap between the achievable pin count and the demand will increase as the technology scales, due to the increasing computation resources and supply current. Pin reduction techniques are thus required for continued computing performance growth. In this article, we propose a chip pin constraint alleviation strategy, through on/off-chip power delivery system co-design, to effectively reduce the demand for power pins. An analytical model of a power delivery system, consisting of on/off-chip regulators and a power delivery network, is proposed to evaluate the influence of regulator design and package conduction loss. By combining this model with a multi-core processor model of performance and memory bandwidth requirements, we characterize the entire multi-core processor system to investigate the relationship between the chip pin constraint and performance in multi-core processor scaling and the effectiveness of our strategy. Experiments show that with the conventional power delivery system design, the chip pin constraint severely limits the performance growth as the technology scales. Using the on/off-chip power delivery system co-design, our strategy achieves a significant pin count reduction, for example, 31.3% at the 8nm technology node, compared to the conventional design with the same chip performance, while, provided with the same chip pin count, it is able to improve, by 35.0%, the chip performance at 8nm compared to the conventional design. For real applications of different parallelism, our strategy outperforms its counterpart, with a 23.7% performance improvement on average at the 8nm technology node.

In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, with in the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling, in that long global interconnect lines become signicantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.Most synchronous digital systems consist of cascaded banks of sequential registers with combinatorial logic between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. The global performance and local timing requirements are satisfied by the careful insertion of pipeline registers into equally spaced time windows to satisfy critical worst case timing constraints. The proper design of the clock distribution network ensures that these critical timing requirements are satisfied and that no race conditions exist.The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network. Interrelationships among these three subsystems of a synchronous digital system are critical to achieving maximum levels of performance and reliability.Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important area of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies.The literature in this field exists in a variety of journals and conference proceedings. Examples include the IEEE Transactions of Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE/ACM Design Automation Conference, and a host of related computer, circuits, and CAD conferences. Survey and review articles exist that summarize many of the primary results while providing background and perspective.