Technology independent boundary scan synthesis (design flow issues)

A boundary scan scheme is introduced that uses multiple-valued logic signaling to reduce the number of chip pins and on-chip control signal lines, which leads to a decrease in the chip area overhead as well as interconnection complexity. The various modes of operation in the proposed scheme are defined by the quaternary control line CS (control signal). Also encoded on CS is the clock signal used to synchronize the data movement in the boundary scan shift register path. The proposed scheme does not allow the application of the clock pulses through BSI during the apply test mode of operation. However, application of clock pulses during this mode has no apparent use since data cannot be shifted out. >

In this paper we present a new BIST test pattern generator architecture and a methodology to program this architecture to generate tests for any given inter-chip interconnect circuitry via IEEE 1149.1 boundary-scan architecture. The test architecture uses two test pattern generators, a C-TPG that generates test patterns for the control cells in the boundary scan chain and a D-TPG that generates rest patterns for the data cells. The other main component of the test architecture is a lookup table which is programmed to select, for each boundary scan cell, a specific C-TPG or D-TPG stage whose content is shifted into that cell. This test architecture provides a complete BIST solution for interconnect testing. The proposed BIST TPG design procedure uses the notions of incompatibility and conditional incompatibility and generates TPG designs that (i) guarantee that no circuit damage can occur due to multi-driver conflicts, (ii) guarantee the detection of all interconnect faults, (iii) have low area overhead, and (iv) have low test length. The proposed procedure is used to obtain TPG designs that require significantly less test time and area than other TPG designs, for eight interconnect circuits extracted from industrial boards.

A new mixed-mode boundary scan architecture is developed. The digital part of this architecture complies with the IEEE Std 1149.1. For the analogue part, we propose a new boundary scan cell design and define 4 analogue test instructions. The control signals for each instruction are also described.

Boundary Scan is being added to the manufacturing test strategy. With no experience, where do you start? An organization venturing into this new territory must adopt changes in Test and Design processes to achieve a successful implementation as an enhancement to board test. Highlighting the benefits for the effort is key to getting buy-in from all groups involved from concept to product, especially the Design group. As experience is gained, less interaction between groups is required to implement Boundary Scan, but that relationship can never be severed without compromising the design or manufacturability. Addressing the issues of Design For Test (DFT) early in a product life-cycle will prevent costly oversights and mistakes. A methodical approach is necessary to design in Boundary Scan testability. Very complex designs can require significant design effort during schematic capture that hardware developers are not accustomed to providing. Often times, complex IC access points for developers share pins with the IEEE 1149.1 Test Access Port (TAP). Care must be taken to prevent a manufacturable Boundary Scan design from disabling a design debug port (and vice versa), requiring close coordination between Test and Development during this phase of the design. In addition, both groups must deal with the requirements for signal integrity so that test and programming time targets can be achieved. Solutions may include dedicated Boundary Scan components designed into the product and test fixture. Upon schematic completion, generation of test and programming vectors follows. (Vectors are the logic bits that are loaded into the Boundary Scan registers – taken from the term for a one-dimensional array.) The Automatic Test Pattern Generator (ATPG) tool must be capable of handling the specific requirements of your design such as programming of persistent memory and management of partitioning devices. Details of vector generation are beyond the scope of this discussion, however care and effort to ensure a match between the design netlist and physical manufacturing to achieve maximum test coverage may require changes to the development and production cycle of a new design and should be considered in scheduling resources. Bringing all of the prior efforts together to test a product doesn't complete the process. Deficient Boundary Scan implementations in ICs and oversights in the design can result in significant delays during the test of initial prototypes, delays that have never been experienced in a test cycle. These must be overcome through interaction with the part suppliers and the design group, and rectified to satisfy test coverage requirements. This method will be explained in generic terms to assist the reader in employing the technique in a product design with specific examples given from the implementation of boundary scan in a dense and complex Motorola Cellular Infrastructure board-set. The shift in test method for Motorola from bed-of-nails to Boundary Scan was intensified by the incorporation of a system-level 1149.1 architecture to re-use designed-in product features for postproduction testing.

It is shown that interconnect testing for boards that mix boundary scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a scan circuitry integrity test, a fairly conventional boundary scan interconnect test, and a test for shorts between the boundary scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains boundary scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor boundary scan access, and that may even repeatedly not be detectable. >

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes. >

The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. A similar standard for analog circuits is yet to be set up. In this paper we propose a new analog boundary scan architecture which is similar to the IEEE Std. 1149.1. The basic analog boundary scan cell, the defined instructions, the associated operations, and the control circuitry are described. The advantages of this architecture include: (1) Signal at various test points can be sampled simultaneously, (2) test stimuli can be injected to various test points simultaneously, and (3) test stimuli loading and test response outputting can be done simultaneously.

As the technology is shrinking and the working frequency is going into the multi Gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically, signal integrity loss issues are becoming more important, and detection and diagnosis of these losses are becoming a great challenge. In this paper, an enhanced boundary scan architecture, with slight modification in the boundary scan cells, is proposed to test signal integrity in SoC interconnects. Our extended JTAG architecture: 1) minimizes scan-in operation by using modified boundary scan cells in pattern generation; and 2) incorporates the integrity loss information within the modified observation cells. To fully comply with the JTAG standard, we propose two new instructions, one for pattern generation and the other for scanning out the captured signal integrity information.

A vertically integrated test methodology has been developed for ASIC testing based on the IEEE 1149.1 Standard Test Interface. A common interface is used to test at the wafer, packaged-chip and board/system levels. The boundary scan JTAG interface is combined with an internal full scan based test technique to provide a uniform test procedure at all stages of testing. At the prototype debug phase, the test circuitry is configured to test for design and process faults. At the manufacturing stage, it allows for efficient wafer sorting and packaged chip testing. At the board/system level, the same test set used at the wafer and package levels can be employed for incoming-inspection of parts and in-circuit-testing. In addition to basic scan testing, the protocol can perform AC/delay-fault testing. For embedded megacell and RAM module testing it is configured to control and operate an independent BIST scheme inside the ASIC device to achieve at-speed testing. This test methodology has been implemented on practical ASIC parts. The area overhead for the boundary scan architecture is on the order of a few percent for 30-50 K gate designs, and depending on the type of implementation, performance overhead varies from minimal to no penalty at the I/O cells.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Click to increase image sizeClick to decrease image sizeKey Words: Bountry scantestablitySystem testProduct quality Additional informationNotes on contributorsMeryem MarzoukiAbout the Authors: Meryem Marzouki received a Ph.D. in computer science from the National Polytechnical Institute of Grenoble in 1991. From 1987 to 1992, she was involved primarily in prototype validation of ICs in the framework of electron-beam testing. Since then, her main research interests have been artificial intelligence approaches for test and diagnosis. Her current work is related to the partial boundary scan board and MCM test and diagnosis, fuzzy logic-based diagnosis of analog devices, and high-level synthesis for testability at the circuit and system levels. Since 1992. she has been a researcher with the CNRS (French National Research Center) in charge of the Diagnosis of Complex System Group al TIMA Laboratory in Grenoble, France.Adam OsseiranAdam Osseiran received a Ph.D. in microelectronics in 1986 from the Polytechnic Institute of Grenoble. He has developed a self-testable microcontroller dedicated to transportation systems. He then joined the Polytechnic Institute of Lausanne (Switzerland) where he was responsible for the design and test center of integrated circuits. His main research interests are in the design and test of mixed-signal integrated circuits. He is one of the two European contact persons to the working group on the standardization of the mixed-signal test bus. He is currently professor of microelectronics at the Engineering School of Geneva.

System-in-Package (SiP) is where multiple dice, along with passive components, are mounted onto a common substrate. For the purposes of testing, the substrate can be viewed as simply a printed circuit board. If viewed as such, there are two IEEE standards that can be used very effectively to provide testing of SiPs, (1) 1149.1 A Test Access Port and Boundary Scan Architecture, and (2) 1149.4 A Standard Mixed Signal Test Bus.

IEEE 1149.7 (Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary Scan Architecture) is a superset of the 1149.1 JTAG interface, which, as previously discussed, has been in use since 1990. The IEEE 1149.7 standard (also known in the past as cJTAG or Compact JTAG, and later as aJTAG or Advanced JTAG due to copyright issues with the name CJTAG) was developed to address some of the known limitations of 1149.1 performance and extend its ­capabilities by creating a complementary standard that addresses the changes in the integrated circuit technology and topology. Originally defined as part the MIPI Test and Bdebug Working Group, 1149.7 defines a hierarchy of new, but JTAG compatible capabilities. With increasing levels of complexity, it replaces the JTAG TAP FSM with alternate TAP.7 architectures to implement additional functionality and maximize debug performance. Like other JTAG extension, a key concern is to maintain backward compatibility with IEEE 1149.1 infrastructure, semiconductor IP, software IP, and existing debug and test tools.

The IBM Corporation's Federal Systems Division (FSD) has designed, developed and implemented a VLSI design methodology selected specifically for the DoD's design environment. The military industry VLSI requirements and IBM FSD's design system goals for developing chip design methodology are described. Substantial reduction in computer costs and design schedule using the methodology and the design system components is demonstrated. The rationale behind selecting the specific combination of tools, from the many design systems in IBM, for forming the FSD chip design system and the methodology is explained.

In a VLSI design environment where a range of chip technologies are available and concurrent chip designs are commonplace, it is not feasible to build a wiring program for each technology. Additionally, a chip's design methodology may demand specific abilities from a wiring program. KWIRE was developed to meet the needs of a multiple-technology, multiple-methodology VLSI design community. It has been used on a range of chips, from small designs to custom microprocessors. Modeling the users' designs and design rules in geometric terms allows KWIRE to handle such a diversity of chip designs. This paper describes the KWIRE system and router.

Single board, and now multi-board testability is highly conditioned by the availability of various forms of boundary scan technology. This paper surveys the three more recent IEEE Standards relating to boundary scan. The paper is based on three backgrounders prepared by members of the individual Working Groups for the IEEE Standards booth at ITC 2003.