Interconnect testing of boards with partial boundary scan

Boundary Scan is being added to the manufacturing test strategy. With no experience, where do you start? An organization venturing into this new territory must adopt changes in Test and Design processes to achieve a successful implementation as an enhancement to board test. Highlighting the benefits for the effort is key to getting buy-in from all groups involved from concept to product, especially the Design group. As experience is gained, less interaction between groups is required to implement Boundary Scan, but that relationship can never be severed without compromising the design or manufacturability. Addressing the issues of Design For Test (DFT) early in a product life-cycle will prevent costly oversights and mistakes. A methodical approach is necessary to design in Boundary Scan testability. Very complex designs can require significant design effort during schematic capture that hardware developers are not accustomed to providing. Often times, complex IC access points for developers share pins with the IEEE 1149.1 Test Access Port (TAP). Care must be taken to prevent a manufacturable Boundary Scan design from disabling a design debug port (and vice versa), requiring close coordination between Test and Development during this phase of the design. In addition, both groups must deal with the requirements for signal integrity so that test and programming time targets can be achieved. Solutions may include dedicated Boundary Scan components designed into the product and test fixture. Upon schematic completion, generation of test and programming vectors follows. (Vectors are the logic bits that are loaded into the Boundary Scan registers – taken from the term for a one-dimensional array.) The Automatic Test Pattern Generator (ATPG) tool must be capable of handling the specific requirements of your design such as programming of persistent memory and management of partitioning devices. Details of vector generation are beyond the scope of this discussion, however care and effort to ensure a match between the design netlist and physical manufacturing to achieve maximum test coverage may require changes to the development and production cycle of a new design and should be considered in scheduling resources. Bringing all of the prior efforts together to test a product doesn't complete the process. Deficient Boundary Scan implementations in ICs and oversights in the design can result in significant delays during the test of initial prototypes, delays that have never been experienced in a test cycle. These must be overcome through interaction with the part suppliers and the design group, and rectified to satisfy test coverage requirements. This method will be explained in generic terms to assist the reader in employing the technique in a product design with specific examples given from the implementation of boundary scan in a dense and complex Motorola Cellular Infrastructure board-set. The shift in test method for Motorola from bed-of-nails to Boundary Scan was intensified by the incorporation of a system-level 1149.1 architecture to re-use designed-in product features for postproduction testing.

Board-level boundary scan testing, focusing largely on the boundary scan EXTEST mode for structural testing of interconnects between boundary scan devices on a board and testing of conventional, nonscan components which cannot be accessed using traditional in-circuit or cluster test techniques, is dealt with. Strategies and test-nail placement for implementing various types of boundary scan testing are detailed. The strategies discussed are virtual interconnect, virtual in circuit, standard cluster testing, and virtual cluster testing. It is shown that, where restricted physical access hampers in-circuit or cluster testing, virtual access provided by boundary scan device leads may offer the means of assuring a comprehensive test. When both physical and virtual access is needed, this requirement must be taken into account during board design and factored into board layout to ensure successful implementation of the test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed. >

In this paper we present a new BIST test pattern generator architecture and a methodology to program this architecture to generate tests for any given inter-chip interconnect circuitry via IEEE 1149.1 boundary-scan architecture. The test architecture uses two test pattern generators, a C-TPG that generates test patterns for the control cells in the boundary scan chain and a D-TPG that generates rest patterns for the data cells. The other main component of the test architecture is a lookup table which is programmed to select, for each boundary scan cell, a specific C-TPG or D-TPG stage whose content is shifted into that cell. This test architecture provides a complete BIST solution for interconnect testing. The proposed BIST TPG design procedure uses the notions of incompatibility and conditional incompatibility and generates TPG designs that (i) guarantee that no circuit damage can occur due to multi-driver conflicts, (ii) guarantee the detection of all interconnect faults, (iii) have low area overhead, and (iv) have low test length. The proposed procedure is used to obtain TPG designs that require significantly less test time and area than other TPG designs, for eight interconnect circuits extracted from industrial boards.

Click to increase image sizeClick to decrease image sizeKey Words: Bountry scantestablitySystem testProduct quality Additional informationNotes on contributorsMeryem MarzoukiAbout the Authors: Meryem Marzouki received a Ph.D. in computer science from the National Polytechnical Institute of Grenoble in 1991. From 1987 to 1992, she was involved primarily in prototype validation of ICs in the framework of electron-beam testing. Since then, her main research interests have been artificial intelligence approaches for test and diagnosis. Her current work is related to the partial boundary scan board and MCM test and diagnosis, fuzzy logic-based diagnosis of analog devices, and high-level synthesis for testability at the circuit and system levels. Since 1992. she has been a researcher with the CNRS (French National Research Center) in charge of the Diagnosis of Complex System Group al TIMA Laboratory in Grenoble, France.Adam OsseiranAdam Osseiran received a Ph.D. in microelectronics in 1986 from the Polytechnic Institute of Grenoble. He has developed a self-testable microcontroller dedicated to transportation systems. He then joined the Polytechnic Institute of Lausanne (Switzerland) where he was responsible for the design and test center of integrated circuits. His main research interests are in the design and test of mixed-signal integrated circuits. He is one of the two European contact persons to the working group on the standardization of the mixed-signal test bus. He is currently professor of microelectronics at the Engineering School of Geneva.

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.

System-in-Package (SiP) is where multiple dice, along with passive components, are mounted onto a common substrate. For the purposes of testing, the substrate can be viewed as simply a printed circuit board. If viewed as such, there are two IEEE standards that can be used very effectively to provide testing of SiPs, (1) 1149.1 A Test Access Port and Boundary Scan Architecture, and (2) 1149.4 A Standard Mixed Signal Test Bus.

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes. >

The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance.

To reduce total chip production costs, circuits must be more testable. Several design for testability schemes which tradeoff various design parameters have been proposed toward that end. The recently proposed partial reset (PR) method is incorporated. Rather than allowing all memory elements in a sequential circuit to be reset by a primary input, only a subset of them is given the capability to reset. PR has less hardware overhead and typically smaller test application times than scan design, PR, furthermore, allows unrestricted at-speed testing. The tradeoff is in slightly lower testability. A dynamic PR flip flop selection method is described utilizing a fast sequential test generator. The automated system developed in this research works closely with the test generator to insert PR, observability enhancements and partial scan into a given circuit. The result is higher fault coverage than is possible with PR alone and faster test application times than scan design. Results are shown on all ISCAS'89 circuits, up to s9234. Even though multiple runs of test generation is performed, CPU times are comparable to a single run of conventional deterministic automatic test pattern generations.

City walls define the physical and perceptual boundaries of the historic city, characterising both the environment inside the walls and the landscape outside them. From ancient times to the modern era, city walls have played a divisive role: an interruption between the circumscribed settlement and the adjacent territory, separating the limited and known city from the countryside. Initially built to protect the city and make it ‘impervious’ to enemies, when the defensive function of the fortifications ceased, due to the new demands introduced by the contemporary era and the continuous expansion of cities outside the fortified walls, they became an integral part of urban transformations. In addition to the intrinsic ‘impermeability’ of these structures, there are further factors of cognitive inaccessibility due to the loss of continuity resulting from collapses and the erasure of sections due to the superimposition of other structures. Where the circuit of the walls is more intact, however, it can offer new perspectives on the city-palimpsest: in these cases, in fact, the city walls can be understood as permeable filter spaces that redefine the relationship between the historic centre and the external environment. Starting from these premises, through the interpretation of published sources on the physical and cognitive enjoyment of urban walls, this contribution investigates recent experiences of improving and expanding accessibility to fortifications at both national and international level. With particular attention to the Italian and Spanish contexts, the study focuses on design strategies aimed at improving the physical and cognitive accessibility of these unique and fragile heritage sites, reflecting on approaches, operational methods and results, with the aim of exploring specific issues related to restoration and architectural design projects.

Constructing IP cores’ transparency paths for SoC test access using greedy search

IEEE 1149.7 (Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary Scan Architecture) is a superset of the 1149.1 JTAG interface, which, as previously discussed, has been in use since 1990. The IEEE 1149.7 standard (also known in the past as cJTAG or Compact JTAG, and later as aJTAG or Advanced JTAG due to copyright issues with the name CJTAG) was developed to address some of the known limitations of 1149.1 performance and extend its ­capabilities by creating a complementary standard that addresses the changes in the integrated circuit technology and topology. Originally defined as part the MIPI Test and Bdebug Working Group, 1149.7 defines a hierarchy of new, but JTAG compatible capabilities. With increasing levels of complexity, it replaces the JTAG TAP FSM with alternate TAP.7 architectures to implement additional functionality and maximize debug performance. Like other JTAG extension, a key concern is to maintain backward compatibility with IEEE 1149.1 infrastructure, semiconductor IP, software IP, and existing debug and test tools.

In this paper, we present an easily-testable cube-connected cycles (CCC) structure for VLSI/WSI implementation. The concept of boundary scan is used to provide test vectors and capture the resulting responses. A simple design modification is made to considerably reduce the test application time. The test access port of each processing element (PE) is utilized to perform comparisons between PEs. Single-bit comparators are appropriately placed in order to locate faults in the PEs and interconnection links in the CCC structure. The scheme is shown to be simple enough to be practically useful.

In this paper, we propose a methodology for the random testing of interconnects with tri-state nets. A simple yet effective LFSR based impulse random test vector generator is designed to generate desired random vectors which will not activate multiple tri-state drivers with different values. The detail statistical analysis is conducted to derive two simple guidelines for the determination of test hardware configuration and the test length. The results show that the test length is compatible with the deterministic test methods. >