KWIRE: A multiple-technology, user-reconfigurable wiring tool for VLSI

The IBM Corporation's Federal Systems Division (FSD) has designed, developed and implemented a VLSI design methodology selected specifically for the DoD's design environment. The military industry VLSI requirements and IBM FSD's design system goals for developing chip design methodology are described. Substantial reduction in computer costs and design schedule using the methodology and the design system components is demonstrated. The rationale behind selecting the specific combination of tools, from the many design systems in IBM, for forming the FSD chip design system and the methodology is explained.

This special issue is about the methodologies and tools that may help us solve the VLSI design crisis of the 1980s. Basically, there are three approaches. The first school of thought believes that all design decisions should be made solely by the human designer, who has gained experience through good design practices in the last 10 or 20 years. This approach, called computeraided design, gives the designer an "efficient paper and pencil" by providing graphic editors, design verification and simulation tools, and efficient databases. This approach is evolutionary and tends to be bottom up, since building blocks are first designed and then later used to realize higher level structures. The resulting design is of high quality, since humans are very good in optimizing designs. On the other hand, the human designer is slow and error-prone. Furthermore, creative designers optimize design by creating new design rules, thereby creating a demand for new verification tools and design description languages for documentation and communication between designers. After a bried review of the three approaches, the collection of articles presented, depicting all three approaches to VLSI design tools (each representing a different methodology in VLSI design), are briefly summarized.

As the technology node scales down below nanometer, the design rules significantly increase, which in turn results in the huge search problems of the chip design with an early-stage technology. DTCO (Design-Technology Co-Optimization) becomes a key methodology in semiconductor industry to overcome the limitation of physical scaling and transistor density, and to improve performance and power efficiency [1-2]. However, DTCO induces huge increase of design spaces in physical implementation since chip designers should tune the technology related variables along with the conventional design variables at the early technology stage. ML (machine learning) is a powerful technique when tuning and optimizing such complicated parameters in technology and design [3]. Synopsys DSO.ai (Design Space Optimization AI) is an early innovator of ML (Machine Learning) in EDA (Electronic Design Automation) area, where the tool uses advancements of RL (Reinforcement Learning) to effectively search the massive design space for global near-optimal targets [4]. In this paper, we report DSO.ai applications on 3nm technology and designs, such as PPA (Performance-Power-Area) improvements in both HP (high performance) and HD (high density) libraries, NDR (non-default rule) routing on both clock and signal nets, LP (layer promotion), density control, routing wire and via cost tuning, and more. Furthermore, we utilize ML capability in searching and optimizing technology parameters, e.g., key design pitches and design rules, as well as design parameters, e.g., via/wire cost, placeholder densities, legalization and routing strategies, and other EDA settings, to maximize PPA metric and to minimize DRC violation. Our goal is to find the best values of the initial parameters from an early technology and design stages and to encapsulate them in RM (Reference Methodology) script to provide the designer with the mega switch in entire design flows. Parameter range (to be explored) and evaluation metrics (to score QOR) are defined, then DSO.ai explores search spaces and trains itself to minimize the optimization cost. Optimized parameter values are evaluated against the reference parameters to reproduce the benefit across various designs and technology collaterals. In this manner, different parameters can be optimized given design methodology. This iterative process can be extended to optimize all design technology parameters to maximize PPA on 3nm design technology and designs and beyond. Proposed approach applied to optimize achievable core area and improve max frequency, respectively. Design flow with ML-assisted parameter could reproduce improvement across the different size and different styles of the benchmark designs. Optimization for achievable core area could reduce -0.5% at cell-driven design and -0.6% at route-driven design. Optimization for performance could improve the frequency of +1.42% at cell-driven design and +1.43% at route-driven design in Samsung 3nm technology.

VLSI Design Environments investigates design alternatives such as object oriented data modelling. The difficulty of automating chip architecture designs is caused by the complexity of the problem. The explosion of design decions make a heuristic approach necessary. PLAYOUT aims at the solution of system problems based on hierarchy, top-down plannin

Design rule checking (DRC) is an important step in VLSI design in which the widths and spacings of design features in a VLSI circuit layout are checked against the design rules of a particular fabrication process. In the past, some efforts to build hardware accelerators for DRC have been proposed, but these efforts were hobbled by the fact that it is often impractical to build a different rule-checking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. Because the rule-checking is built in configurable hardware, it can garner impressive speedups over software approaches, while retaining the flexibility needed to easily change the rule checker as rules or processes change. Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking; this approach is particularly well-suited to the constraints of configurable hardware. Although design rules do change over time, their intrinsic similarity allows us to propose a general scalable architecture for DRC. We then demonstrate our approach by applying this architecture to a set of design rules for the MOSIS SCN4N SUB process. The hardware required per rule is quite small; we have implemented several design rule checks within a single Xilinx XC4013 FPGA. Our hardware, implemented on a Pamette board, runs at a clock rate of 33 MHz. We also compare the performance of our approach to software methods and demonstrate overall speedups in excess of 25X.

A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed. >

We describe a powerful framework for designing efficient batch algorithms for certain large-scale dynamic problems that must be solved using external memory. The class of problems we consider, which we call colorable eztemaldecomposable problems, include rectangle intersection, orthogonal line segment intersection, range searching, and point location. We are particularly interested in these problems in two and higher dimensions. They have numerous applications in geographic information systems (GIS), spatial databases, and VLSI and CAD design. We present simplied algorithms for problems previously solved by more complicated approaches (such as rectangle intersection), and we present efficient algorithms for problems not previously solved in an efficient way (such as point location and higherdimensional versions of range searching and rectangle intersection). communication is the bottleneck in many large-scale applications such as those arising in VLSI and CAD design, spatial databases, and geographic information systems (GIS). In this paper we consider I/O-efficient algorithms for batched searching problems. We consider both batched static and batched dynamic problems, and use the correspondence which often exists between a ddimensional static problem and a (dl)-dimensional dynamic problem to obtain a number of new d-dimensional algorithms. We give experimental results concerning the running time for our approach applied to the red-blue rectangle intersection problem, which is a key component of the extremely important database operation spatial join. Our algorithm scales well with the problem size, and for large problems sizes it greatly outperforms the well-known sweepline approach. One prominent example of the problems we consider is the rectangle intersection problem, which is a key component in VLSI design rule checking [31] and in the extremely important database operation spatial join [34]. We illustrate the practical significance of our algorithms by comparing the empirical performance of our algorithm for this problem with the well-known sweepline algorithm developed for internal memory. 1.1 Problem definition and memory model

ITT has developed and implemented a flexible CAD system strategy which solves major problems in integrating VLSI design aids. The complexity of current generation VLSI CAD and the proliferation of commercial and internally generated design aids necessitates a coordinated approach to CAD system integration. This need was recognized early at ITT where it is compounded by a multi-national design environment comprising 14 major VLSI design centers and a growing number of smaller design centers each with its own specific set of needs and constraints. The CAD system integration strategy described achieves flexibility through a neutral data format tool interface architecture, a software language standard, and multi-source-able design rules. The paper describes the strategy and the semi-custom and full custom design systems developed following the strategy.

DDI (data direct implementation) approach for pattern discrimination chips is proposed, and its specified design methodology is presented. In the design, pattern data are transformed to a truth table and the table is generalized to adapt the unknown pattern data. The generalization operator is chosen by using a genetic algorithm (GA). The generalized, or evolved truth table is then synthesized to logic circuits. This evolvable chip design methodology is realized by the high integration density of the current reconfigurable VLSIs. We have developed a prototype of the evolvable sonar discrimination chip. The prototype demonstrates higher discrimination accuracy and higher processing speed than conventional approaches. Furthermore, it shows high fault tolerance against stuck-gate faults, which is not achieved with the ordinary processor based hardware.

Detailed routing becomes a crucial challenge in VLSI design with shrinking feature size and increasing design complexity. More complicated design rules were added to guarantee manufacturability, which made detailed routing an even harder task to achieve in the design flow. In this paper, we propose a detailed router that judiciously handles hard-to-access pins and new design rules including length-dependent parallel run length spacing, end-of-line spacing with parallel edges, and corner-to-corner spacing. Our experimental results show that our framework can effectively reduce the number of violations with comparable wirelength. Comparing our algorithm with the best score of each released designs in the ISPD'19 Contest, there is 2% score improvement. Compared with the state-of-the-art work, our algorithm achieves 69% better scores. The source code of Dr. CU 2.0 is available at https://github.com/cuhk-eda/dr-cu.

Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV/sup 2/ rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these charge-recovering systems approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in the hundreds of MHz with relatively low overhead. Among other charge-recovery designs, researchers have demonstrated microcontrollers, standard-cell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multiGHz clock networks. In this paper, we present an overview of the field and focus on two chip designs that highlight some of the promising charge recovering techniques in practice.

The paper describes the authors experience in using two major design suites currently on offer through the EuroChip program, namely, Mentor Graphic's Genesil and Cadence's Edge, for second year design projects. The goal was to design a simple self-learning neural network system based on a multiprocessor architecture for pattern classification applications. The overall objective of the projects was to bring together the various disciplines of the undergraduate course in information system engineering (ISE) including computing, circuit design, chip design and algorithms, in the form of a design project. The authors' experience suggests that as well as improving the VLSI design skills of students, VLSI design tools can bring benefits such as teaching system design and group interactions.

In VLSI design, the utilization of Design Rule Check (DRC) tools in the early stage is crucial for predicting and resolving violations, thereby expediting the physical design process. In our study, we present an efficient model that predicts DRC violations prior to the routing stage. Additionally, our model incorporates a sliding-window technique to enhance the feature extraction process. We extract structural features using Graph Convolutional Networks and utilize feature reuse techniques to fully recover the lost information in neural layers, which serves as input to the Convolutional Neural Network model, resulting in more accurate hotspot prediction. The experimental results demonstrate that our model successfully identifies 95.78% of DRC violations, with a mere 4.17% false-alarm rate. Not only does our method deliver improved feature preprocessing results, but it also enhances prediction accuracy compared to alternative approaches.

The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford University and Texas Instruments in a 1.5 V 0.15 /spl mu/m process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.

PurposeThe generic design environment for a flexible printed‐circuit board assemblies (PCBA) remanufacturing cell contains four interrelated complex design domains. Mechanical design domains are really complex and the use of well‐proven mechanical product design methodologies does not help the designer. Hence, this paper aims to develop a generic systematic design methodology for a flexible PCBA remanufacturing cell.Design/methodology/approachThe study investigates the use of conventional mechanical product design techniques for the design of a flexible PCBA rework (remanufacturing) cell. It indicates problems and the weaknesses when conventional product design techniques are used for the development of flexible manufacturing systems (FMS). It then provides a new systematic mechanical design methodology for designing a flexible PCBA rework (remanufacturing) cell. The design methodology is intended to be generic in order to apply successfully to any FMS design.FindingsConventional product design methodology cannot be used directly for the design of a flexible PCBA remanufacturing cell. Hence, two design methodologies were developed: the generic FMS mechanical design methodology and a specific FMS design methodology for a PCBA rework cell. The first one was developed based on the tasks of the conventional product design process integrated with new design tools. The generic design methodology was then extended to obtain the second methodology for a PCBA rework cell design. Both of the methodologies were applied to a flexible PCBA rework cell design problem. Both design methodologies eliminated unusable design solutions at the early design stages of the conceptual design process and made the design process easier.Practical implicationsThe generic and specific design methodologies provide a better design environment, even for less specialized FMS designers.Originality/valueThe design methodologies may help for the commercialization of a flexible PCBA remanufacturing cell that may be used for SM rework and assembly.