A Class-C 3-phase CMOS Capacitive-Coupled VCO

Internet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm2. The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of −116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is −107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 μW from 0.6 V supply voltage, making it suitable for ultra low power applications.

In this paper, a 24GHz frequency source for low phase noise is presented in a 0.18µm CMOS process. The 24GHz frequency source chip is composed of a 12GHz voltage controlled oscillator (VCO) and a 24GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17dBc/Hz at a 1MHz offset frequency and -20.95dB at 23.19GHz frequency, respectively. The measured frequency tuning range is from 23.19GHz to 24.76GHz drawing 2.72mA at a supply voltage of 1.8V not including an output buffer.

In this thesis, design of the voltage controlled oscillator (VCO) in radio frequency system is presented. The circuits discussed in this thesis are design to operate at different frequencies and they are implemented by using different process technologies. For individual circuit, we describe its structure and principles, and finally discuss the results of simulation and measurement. In Chapter two, a Colpitts differential VCO circuit is designed, in which, the gm-boosting transistors are used to increase the value of its transconductance and to reduce the required start-up current. The feedback capacitor divider can also increase the output amplitude and improve the performance. The measured oscillation frequencies are from 2.66GHz to 2.72GHz, and the measured phase noise is -113dBc/Hz @ 1MHz frequency offset. In Chapter three, we present a complementary low power VCO circuit design. The complementary structure can increase the value of transconductance, thus it can increase transistor switching speed and reduce the power consumption. Furthermore, the second harmonic of the tail current source is filtered out by using the noise filter technique. The measured oscillation frequencies are from 2.12GHz to 2.74GHz, and the measured phase noise is -102dBc/Hz @ 1MHz frequency offset. The measured power consumption is 11.84mW. The content of Chapter four is a 60GHz VCO which is mainly designed by using microstrip lines. The use of addition cross couple pair and transmission lines increase the transconductance, and the microstrip lines need to be selected as appropriate length to achieve the best performance. In addition, we also used the source degenerated capacitance technique to increase the oscillation frequency and the tuning range. The simulated center oscillation frequency is 61.23GHz, and the phase noise is -96dBc/Hz @ 1MHz frequency offset. The tuning range is 59.9GHz-62.36GHz.

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

This study presents an ultra-low-power, low-phase noise, and small-size voltage-controlled ring oscillator for use in implantable electronics operating in the Medical Implant Communication Service (MICS) frequency band and 65-nm IBM CMOS technology. This five-stage voltage-controlled ring oscillator does not require external inductor and capacitor similar to other LC oscillators, and hence, requires very small die area. A new methodology to design them has been employed in this study, and for optimizing the design of this voltage-controlled oscillator (VCO), the phase noise and power consumption of five-stage ring oscillators have been formulated and simulated for different sizes of transistors. The simulated phase noise of this VCO was -111 dBc/Hz at 1 MHz offset from a 400-MHz center frequency. The power consumption of VCO was 158 μW. This VCO has a tuning range from 352 to 454 MHz for tuning within the MICS band frequency, and frequency correction accounts for process supply voltage and temperature effects.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

ABSTRACTThe circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is −110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about −1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about −180.7 and −191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.

A sub-1 V 1.6 GHz voltage-controlled oscillator (VCO) was designed and fabricated using 0.35 μm CMOS technology. This LC-based VCO can operate at a supply voltage as low as 0.8 V. A top-biased PMOS, with capacitor connected in parallel, is used in order to reduce the noise contribution in the oscillated frequency even at low voltage supply. Moreover, an accumulation MOS varactor is adopted to provide 29% wider tuning frequency range compared with a diode varactor under same full tuning voltage. With a 0.8 V supply, this 1.6 GHz top-biased A-MOS VCO consumes 9 mW, included output buffer, with a measured phase noise of ?109.3 dBc/Hz @ 600 kHz offset.

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is －107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is －193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

This article presents a low‐power current‐reused voltage‐controlled oscillator (VCO) with a decoupling capacitance. The proposed VCO applies a decoupling capacitance between the power supply and degeneration resistance in the VCO to reduce the unbalanced characteristics of the current‐reused VCO. Adopting the decoupling capacitance can balance and enlarge the output amplitude while enhancing the phase noise. The simulated amplitude unbalance ratio is 5%, compared with 11% of the amplitude unbalance ratio of a conventional current‐reused VCO. In addition, the proposed design enlarges the amplitude by 25%, compared with the amplitude of a conventional current‐reused VCO without increasing power consumption. The proposed design has been fabricated in a TSMC 0.18‐μm CMOS process. The power consumption is 1.6 mW from a 1.8 V supply. The fabricated VCO operates from 2.1 to 2.7 GHz with a 22.7% tuning range. The measured phase noise is −121 dBc/Hz at 1 MHz offset at 2.2 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1626–1629, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26904

A wide tuning range voltage controlled oscillator (VCO) with novel architecture is proposed in this work. The entire circuit consists of a VCO core, a summing circuit, a single-ended to differential (STD) converter and a buffer amplifier. The VCO core oscillates at half the desired frequency and the second harmonic of the VCO core is extracted by the summing circuit, which is then converted to a differential pair by the STD. The entire VCO circuit operates from 58.85 to 70.85 GHz with 20% frequency tuning range. The measured VCO gain is less than 1.6 GHz/V. The measured phase noise at 3 MHz offset is less than -78 dBc/Hz across the entire tuning range. The differential phase error of the output signals is measured by down converting the VCO output signals to low gigahertz frequency using an on-chip mixer. The measured differential phase error is less than 8°. The VCO circuit, which is constructed using 0.35 μm SiGe technology, occupies 770 × 550 μm 2 die area and consumes 62 mA under 3.5 V supply.

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

In this article, a three-stage and five-stage voltage-controlled oscillator (VCO) using current starved configuration has been proposed. Among the two, only a three-stage VCO gives the required bandwidth of 5 GHz. Current starved VCO is designed using complementary metal oxide semiconductor (CMOS) technology. The oscillating output frequency bandwidth (2–7 GHz) is considered as the main objective for the proposed circuit. The proposed three-stage VCO circuit uses low supply voltage of 1 V, low power of 29.93 uW. Transient analysis and periodic steady state (PSS) analysis are performed, and after simulation, a wide frequency bandwidth of 5 GHz was obtained. The phase noise for the three-stage VCO at 1 GHz is −132 dBc/Hz. The circuit has been designed in Cadence Virtuso using gpdk 45 nm CMOS technology with supply voltage of 1 V.