24GHz CMOS Frequency Source with Differential Colpitts Structure-Based Complementary VCO for Low Phase Noise

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

This article presents a low‐power current‐reused voltage‐controlled oscillator (VCO) with a decoupling capacitance. The proposed VCO applies a decoupling capacitance between the power supply and degeneration resistance in the VCO to reduce the unbalanced characteristics of the current‐reused VCO. Adopting the decoupling capacitance can balance and enlarge the output amplitude while enhancing the phase noise. The simulated amplitude unbalance ratio is 5%, compared with 11% of the amplitude unbalance ratio of a conventional current‐reused VCO. In addition, the proposed design enlarges the amplitude by 25%, compared with the amplitude of a conventional current‐reused VCO without increasing power consumption. The proposed design has been fabricated in a TSMC 0.18‐μm CMOS process. The power consumption is 1.6 mW from a 1.8 V supply. The fabricated VCO operates from 2.1 to 2.7 GHz with a 22.7% tuning range. The measured phase noise is −121 dBc/Hz at 1 MHz offset at 2.2 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1626–1629, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26904

A fully integrated and differential AlInAs/InGaAs/InP DHBT voltage controlled oscillator (VCO) with wide tuning range and integrated divide-by-2 static divider was demonstrated for 44 GHz wireless and optical communication applications. To our knowledge, these 44 GHz ICs are the highest frequency fundamental mode fully integrated and differential VCOs with wide tuning range ever reported. The 44 GHz fundamental VCO delivers a typical differential output power of +4 dBm at a center frequency of 44 GHz with a tuning range of up to 4.5 GHz. The measured phase noise shows better than -100 dBc/Hz at 1 MHz offset and better than -80 dBc/Hz at 100 kHz offset. We have achieved more than 6 dB improvement in phase noise performance over the differential SHBT VCO results that we reported last year (A. Kurdoghlian et al., IEEE GaAs IC Symp. Dig., pp. 129-132, 2001).

Internet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm2. The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of −116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is −107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 μW from 0.6 V supply voltage, making it suitable for ultra low power applications.

An optimization technique for a low phase noise CMOS LC VCO is proposed. The combination of harmonic tuning and on-chip filtering improves both 1/f/sup 3/ and 1/f/sup 2/ phase noise more than 10 dB over a comparable reference VCO. A 2.7 V, 5.4 mA, 30% tuning range, 1 GHz voltage controlled oscillator (VCO) is designed with the technique and implemented in a 0.35 /spl mu/m CMOS process. The optimized 1 GHz CMOS differential VCO achieves -89 dBc/Hz, -116 dBc/Hz and -135 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset frequencies from the carrier, respectively.

In this thesis, design of the voltage controlled oscillator (VCO) in radio frequency system is presented. The circuits discussed in this thesis are design to operate at different frequencies and they are implemented by using different process technologies. For individual circuit, we describe its structure and principles, and finally discuss the results of simulation and measurement. In Chapter two, a Colpitts differential VCO circuit is designed, in which, the gm-boosting transistors are used to increase the value of its transconductance and to reduce the required start-up current. The feedback capacitor divider can also increase the output amplitude and improve the performance. The measured oscillation frequencies are from 2.66GHz to 2.72GHz, and the measured phase noise is -113dBc/Hz @ 1MHz frequency offset. In Chapter three, we present a complementary low power VCO circuit design. The complementary structure can increase the value of transconductance, thus it can increase transistor switching speed and reduce the power consumption. Furthermore, the second harmonic of the tail current source is filtered out by using the noise filter technique. The measured oscillation frequencies are from 2.12GHz to 2.74GHz, and the measured phase noise is -102dBc/Hz @ 1MHz frequency offset. The measured power consumption is 11.84mW. The content of Chapter four is a 60GHz VCO which is mainly designed by using microstrip lines. The use of addition cross couple pair and transmission lines increase the transconductance, and the microstrip lines need to be selected as appropriate length to achieve the best performance. In addition, we also used the source degenerated capacitance technique to increase the oscillation frequency and the tuning range. The simulated center oscillation frequency is 61.23GHz, and the phase noise is -96dBc/Hz @ 1MHz frequency offset. The tuning range is 59.9GHz-62.36GHz.

This letter presents a 3-phase class-C current reused voltage controlled oscillator (VCO). The prototype 5 GHz VCO in 0.18 μm CMOS process is implemented to generate signal with 3 output phases and it uses three identical single-ended current reused VCOs in a ring configuration. A dynamic bias circuit is used to reduce the power consumption, and the back-gate BJTs in PMOSFETs are used as a phase coupling device, the circuit oscillates from 4.48 GHz to 5.1 GHz and the power consumption is 3.53 mW at 1.0 V supply voltage. The measured phase noise is −116.52 dBc/Hz at 1 MHz offset frequency from 5.08 GHz. The VCO occupies a chip area of 1.0 × 0.72 mm2and provides a figure of merit of −185.16 dBc/Hz.

This study presents an ultra-low-power, low-phase noise, and small-size voltage-controlled ring oscillator for use in implantable electronics operating in the Medical Implant Communication Service (MICS) frequency band and 65-nm IBM CMOS technology. This five-stage voltage-controlled ring oscillator does not require external inductor and capacitor similar to other LC oscillators, and hence, requires very small die area. A new methodology to design them has been employed in this study, and for optimizing the design of this voltage-controlled oscillator (VCO), the phase noise and power consumption of five-stage ring oscillators have been formulated and simulated for different sizes of transistors. The simulated phase noise of this VCO was -111 dBc/Hz at 1 MHz offset from a 400-MHz center frequency. The power consumption of VCO was 158 μW. This VCO has a tuning range from 352 to 454 MHz for tuning within the MICS band frequency, and frequency correction accounts for process supply voltage and temperature effects.

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

A new switched-inductor voltage controlled oscillator (VCO) scheme based on tapped vertical solenoid inductors is presented. With tapping ports, various effective inductances are selected by switches for multi-band operation. As a proof of concept, two VCOs, with one and two tapping ports separately, are implemented in a 0.18 µm 1P6M standard CMOS. Because of the vertical structure of the inductors, the new scheme consumes much less area than the conventional switch-inductor VCOs. The measured frequency bands of the VCOs are located between 1.96 and 3.49 GHz, and the measured phase noise at 1 MHz offset is between −115.4 and −118.5 dBc/Hz across all bands under power consumption of 14.4 mW (8 mA, 1.8 V).

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

This paper presents a voltage-controlled oscillator (VCO) with low phase noise by employing the CMOS field-plate (FP) transistors. The proposed FP transistors perform the improvement in flicker noise (1/f noise) was demonstrated in our previous investigation. A complete large-signal model for FP transistors was established by modified BSIM4 model with lossy substrate networks. The proposed 12-GHz VCO with FP transistors was designed and fabricated in TSMC 0.13-mum CMOS process. The measured characteristic of phase noise is -122 dBc/Hz at 1-MHz offset frequency. Compare with a conventional VCO, this novel design shows that the proposed VCO achieves lower phase noise about 5 dBc at offset frequency from 100-kHz to 1-MHz.

A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is －107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is －193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.

To design a multi standard and a multi band transceiver, a quadrature voltage controlled oscillator (VCO), which has a wide tuning range, is essential, while providing low phase noise with low current consumption. In this paper, a dual band quadrature VCO in 0.18 mum CMOS process is presented. To accomplish dual band operation, reconfigurable LC tank is adopted. Series coupling transistors are attached to generate quadrature phase signal with low power consumption and low phase noise. To improve phase noise performance, current sources are eliminated and a filter inductor at the common source node is added. The measured phase noises of low frequency mode and high frequency mode are -101.81 dBc/Hz and -100.59 dBc/Hz at 10 kHz offset frequency; and -123.83 dBc/Hz and -115.06 dBc/Hz at 1 MHz offset frequency and figure of merit (FoM) at 1 MHz offset frequency of -181.8 dB and -180.5 dB with 4 mA current consumption with a 1.7 V supply.

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.