Switched-inductor VCO based on tapped vertical solenoid inductors

In this paper, a 24GHz frequency source for low phase noise is presented in a 0.18µm CMOS process. The 24GHz frequency source chip is composed of a 12GHz voltage controlled oscillator (VCO) and a 24GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17dBc/Hz at a 1MHz offset frequency and -20.95dB at 23.19GHz frequency, respectively. The measured frequency tuning range is from 23.19GHz to 24.76GHz drawing 2.72mA at a supply voltage of 1.8V not including an output buffer.

This article presents a low‐power current‐reused voltage‐controlled oscillator (VCO) with a decoupling capacitance. The proposed VCO applies a decoupling capacitance between the power supply and degeneration resistance in the VCO to reduce the unbalanced characteristics of the current‐reused VCO. Adopting the decoupling capacitance can balance and enlarge the output amplitude while enhancing the phase noise. The simulated amplitude unbalance ratio is 5%, compared with 11% of the amplitude unbalance ratio of a conventional current‐reused VCO. In addition, the proposed design enlarges the amplitude by 25%, compared with the amplitude of a conventional current‐reused VCO without increasing power consumption. The proposed design has been fabricated in a TSMC 0.18‐μm CMOS process. The power consumption is 1.6 mW from a 1.8 V supply. The fabricated VCO operates from 2.1 to 2.7 GHz with a 22.7% tuning range. The measured phase noise is −121 dBc/Hz at 1 MHz offset at 2.2 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1626–1629, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26904

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

This study presents an ultra-low-power, low-phase noise, and small-size voltage-controlled ring oscillator for use in implantable electronics operating in the Medical Implant Communication Service (MICS) frequency band and 65-nm IBM CMOS technology. This five-stage voltage-controlled ring oscillator does not require external inductor and capacitor similar to other LC oscillators, and hence, requires very small die area. A new methodology to design them has been employed in this study, and for optimizing the design of this voltage-controlled oscillator (VCO), the phase noise and power consumption of five-stage ring oscillators have been formulated and simulated for different sizes of transistors. The simulated phase noise of this VCO was -111 dBc/Hz at 1 MHz offset from a 400-MHz center frequency. The power consumption of VCO was 158 μW. This VCO has a tuning range from 352 to 454 MHz for tuning within the MICS band frequency, and frequency correction accounts for process supply voltage and temperature effects.

In this thesis, design of the voltage controlled oscillator (VCO) in radio frequency system is presented. The circuits discussed in this thesis are design to operate at different frequencies and they are implemented by using different process technologies. For individual circuit, we describe its structure and principles, and finally discuss the results of simulation and measurement. In Chapter two, a Colpitts differential VCO circuit is designed, in which, the gm-boosting transistors are used to increase the value of its transconductance and to reduce the required start-up current. The feedback capacitor divider can also increase the output amplitude and improve the performance. The measured oscillation frequencies are from 2.66GHz to 2.72GHz, and the measured phase noise is -113dBc/Hz @ 1MHz frequency offset. In Chapter three, we present a complementary low power VCO circuit design. The complementary structure can increase the value of transconductance, thus it can increase transistor switching speed and reduce the power consumption. Furthermore, the second harmonic of the tail current source is filtered out by using the noise filter technique. The measured oscillation frequencies are from 2.12GHz to 2.74GHz, and the measured phase noise is -102dBc/Hz @ 1MHz frequency offset. The measured power consumption is 11.84mW. The content of Chapter four is a 60GHz VCO which is mainly designed by using microstrip lines. The use of addition cross couple pair and transmission lines increase the transconductance, and the microstrip lines need to be selected as appropriate length to achieve the best performance. In addition, we also used the source degenerated capacitance technique to increase the oscillation frequency and the tuning range. The simulated center oscillation frequency is 61.23GHz, and the phase noise is -96dBc/Hz @ 1MHz frequency offset. The tuning range is 59.9GHz-62.36GHz.

A wide tuning range voltage controlled oscillator (VCO) with novel architecture is proposed in this work. The entire circuit consists of a VCO core, a summing circuit, a single-ended to differential (STD) converter and a buffer amplifier. The VCO core oscillates at half the desired frequency and the second harmonic of the VCO core is extracted by the summing circuit, which is then converted to a differential pair by the STD. The entire VCO circuit operates from 58.85 to 70.85 GHz with 20% frequency tuning range. The measured VCO gain is less than 1.6 GHz/V. The measured phase noise at 3 MHz offset is less than -78 dBc/Hz across the entire tuning range. The differential phase error of the output signals is measured by down converting the VCO output signals to low gigahertz frequency using an on-chip mixer. The measured differential phase error is less than 8°. The VCO circuit, which is constructed using 0.35 μm SiGe technology, occupies 770 × 550 μm 2 die area and consumes 62 mA under 3.5 V supply.

Internet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm2. The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of −116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is −107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 μW from 0.6 V supply voltage, making it suitable for ultra low power applications.

This letter presents a 3-phase class-C current reused voltage controlled oscillator (VCO). The prototype 5 GHz VCO in 0.18 μm CMOS process is implemented to generate signal with 3 output phases and it uses three identical single-ended current reused VCOs in a ring configuration. A dynamic bias circuit is used to reduce the power consumption, and the back-gate BJTs in PMOSFETs are used as a phase coupling device, the circuit oscillates from 4.48 GHz to 5.1 GHz and the power consumption is 3.53 mW at 1.0 V supply voltage. The measured phase noise is −116.52 dBc/Hz at 1 MHz offset frequency from 5.08 GHz. The VCO occupies a chip area of 1.0 × 0.72 mm2and provides a figure of merit of −185.16 dBc/Hz.

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

In this paper, the design and characterization of fundamental voltage controlled oscillators (VCOs) operating in the range from 138 to 146 GHz (VCO-I) and 150.8 to 158.3 GHz (VCO-II) are presented. Both VCO-I and Π are based on Colpitts topology. Additionally, a frequency divider chain (with a divide ratio 8) is added in front of the VCO-I for the sake of precise frequency and phase noise measurements. The simulation results show that the dividers chain is working over a wide frequency range from 60 to 175 GHz. The measured phase noise for both VCOs is -85 dBc/Hz at an offset of 2 MHz. The DC power consumed by each of the VCO is 58 mW from -3 V supply. Both VCO-I and II can deliver maximum power of -3.5 dBm at 146 GHz and 158.3 GHz, respectively. The circuits are fabricated in IHP 0.13 μm SiGe BiCMOS technology with ft and fmax of 300 GHz and 500 GHz, respectively.

This work presents a new structure of center tap (CT) inductor to improve the performance of Ku-band voltage-controlled oscillators (VCOs). Conventional CT inductor provided by the foundry suffers from a poor-quality (Q-) factor large area and low self-resonance frequency. These problems are solved by introducing a coupling structure. For the proposed CT inductor, despite its size is miniaturized by 51%, the Q-factor is increased by 41% in the frequency range of 5-30 GHz compared to a conventional CT inductor. The measured differential inductance and quality factor of the proposed inductor are 385 pH and 22 at 12 GHz. The proposed CT inductor is used to design a compact and wide-tuning-range VCO at Ku-band in 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology, and this leads to 5.8 dB phase noise improvement compared to the use of a conventional CT inductor. The fabricated VCO has a compact core size of 140 μm × 400 μm only. The VCO chip oscillates from 11.7 to 13.7 GHz. The measured phase noise is -107.7 dBc/Hz at 1-MHz offset frequency at a carrier frequency of 13.7 GHz, and the dc power consumption of the VCO core is 4 mW which results in a figure of merit (FoM) normalized to the die area (FoMA) to be -197 dBc/Hz.

This paper presents a voltage-controlled oscillator (VCO) with low phase noise by employing the CMOS field-plate (FP) transistors. The proposed FP transistors perform the improvement in flicker noise (1/f noise) was demonstrated in our previous investigation. A complete large-signal model for FP transistors was established by modified BSIM4 model with lossy substrate networks. The proposed 12-GHz VCO with FP transistors was designed and fabricated in TSMC 0.13-mum CMOS process. The measured characteristic of phase noise is -122 dBc/Hz at 1-MHz offset frequency. Compare with a conventional VCO, this novel design shows that the proposed VCO achieves lower phase noise about 5 dBc at offset frequency from 100-kHz to 1-MHz.

Abstract. In this paper a low-power low-phase-noise voltage-controlled-oscillator (VCO) has been designed and, fabricated in 0.25 μm SiGe BiCMOS process. The resonator of the VCO is implemented with on-chip MIM capacitors and a single aluminum bondwire. A tail current filter is realized to suppress flicker noise up-conversion. The measured phase noise is −126.6 dBc/Hz at 1 MHz offset from a 7.8 GHz carrier. The figure of merit (FOM) of the VCO is −192.5 dBc/Hz and the VCO core consumes 4 mA from a 3.3 V power supply. To the best of our knowledge, this is the best FOM and the lowest phase noise for bondwire VCOs in the X-band. This VCO will be used for satellite communications.

In this paper, a 1-V 3.8 - 5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0 - 1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being upconverted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 - 2.7-mW, depending on the center frequency, and the buffered output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.

ABSTRACTThe circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is −110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about −1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about −180.7 and −191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.