A CMOS receiver with single RF channel for SMILE applications

This paper proposes a single-channel, multi-functional millimeter-wave (mm-Wave) beamforming IC. Designed in a 65 nm CMOS process, the proposed IC operates at 28 GHz and integrates a reconfigurable single RF channel for both transmit (TX) and receive (RX) modes. This channel incorporates a power amplifier (PA) and a low-noise amplifier (LNA) for TX and RX paths, respectively. Notably, the IC features integrated 5-bit digital step attenuators and 6-bit digital phase shifters for precise amplitude and phase control in both TX and RX chains. The digital step attenuator offers a 15.5 dB control range with 0.5 dB steps, while the digital phase shifter provides 360-degree phase control with 5.625-degree steps. The proposed beamforming IC achieves a gain of 29.6 dB in the transmitting RF channel and 22.1 dB in the receiving RF channel.

This paper presents a 77 GHz Receiver (Rx) for automotive radar with high linearity, low noise figure (NF) and reconfigurable gain and bandwidth of the analog baseband (ABB), implemented in TSMC 65 nm CMOS general purpose (GP) technology. The Rx includes a low-noise amplifier (LNA), sharing the transconductance stage with a double-balanced mixer, an LO chain with a frequency doubler and an analog baseband. The entire Rx consumes 123 mW. Measurement results show that the input 1 dB compression point (P 1dB ) is −14 dBm at 81 GHz, a conversion gain (CG) of 20.5–62.5 dB is digitally tunable at 77 GHz, and an NF of 11.2–18.3 dB is achieved over the frequency range of 76–81 GHz.

Noise factor (NF) is used to quantify the degradation of the signal passing through RF circuits. The spot NF widely used in narrow band low-noise amplifier (LNA) is frequency dependent. It's necessary to redefine the NF for the wideband LNA where the ultra-wideband (UWB) signal pulse is assumed to be of the Gaussian pulse. The average NF suitable for the wideband LNA is discussed firstly. Numerical study on the average NF of LNA for UWB impulse radio is presented in this paper. The average NF is analyzed to quantify the relationship between LNA and Gaussian pulse. A design strategy is suggested that the Gaussian pulse frequency response is optimized to lower average NF. The average NF is equivalent to the spot NF when narrow band assumption is made. For wideband systems with constant frequency response, the average NF is determined by two endpoints frequency summation

Low-Noise Amplifier (LNA) plays a crucial part in Radio Frequency (RF) front-end architecture. This paper mainly focuses on designing LNA for Indian Regional Navigation Satellite System (IRNSS) receiver. IRNSS operates on two frequency bands (L5 and S band) and this design is proposed for S band with the center frequency of 2492.028 MHz. Cascode topologies are considered to be conventional ones and they provide higher gain and better reverse isolation. Four different approaches of single-stage cascode topology, such as Common Source (CS) cascode, Common Gate (CG) cascode, shunt-resistive feedback cascode and current reuse cascode, were designed and their performance metrics, based on gain, Noise Figure (NF), return losses and stability, are presented. Focused on the gain and noise figure improvements, Common Source (CS) cascode with interstage series LC circuit LNA was designed and optimized with input and output matching circuitries. The proposed optimized circuit uses current reuse technique along with CS stage to improve the power gain and to achieve low-noise figure. The interstage LC circuit is mainly implemented to act as a tuning circuit to achieve a narrow range of frequency. The proposed work is simulated using 180 nm CMOS technology Generic Process Design Kit (GPDK) and achieve a power gain (S21) of 24.89, 0.994 dB NF, −16.2 dB input return loss (S11) and −11.06 dB output return loss (S22), with higher reverse isolation around −30.47 dB at 1.8 V power supply.

Low-noise amplifiers (LNAs) are one of the important building blocks of wireless receivers. LNA design parameters such as gain, noise figure, linearity, input matching, and stability are important metrics and typically affect the overall performance of the receiver. The strong trade-offs among these design parameters often necessitate several design iterations. While many of these trade-offs are due to the nature of the circuit and are inevitable, it is desirable to decouple the effects of each parameter on the others. In this work, body biasing is introduced as a technique to enhance the linearity, to improve the noise figure and to provide gain variation. These techniques are presented in the context of a three-stage LNA. By applying body biasing in each stage, noise figure, gain variation and linearity of the overall amplifier are adjusted almost independently, i.e., with minimal interrelation among these design parameters. As a proof-of-concept, a prototype 4.4-GHz LNA is designed and fabricated in a 0.13- μm CMOS technology. The LNA achieves a minimum noise figure of 3.8 dB, maximum gain of 20.2 dB, and a maximum IIP3 of -14 dBm while consuming 3.6 mW from a 1.2 V supply.

In ATSC 3.0 physical layer standard, a layered division multiplexing (LDM) scheme has newly accepted as one of the multiplexing schemes in order to improve the reception performance when multiple broadcasting contents are simultaneously delivered through a single RF channel. This paper presents comparison results of LDM and time division multiplexing (TDM) schemes under fixed reception environments, and analyzes the performance gain of LDM over TDM. From the field test results, it was confirmed that the LDM gain in the theoretical analysis is still maintained in the actual field.

The purpose of this paper is to design a microwave monolithic integrated circuit (MMIC) for low noise amplifier (LNA) X-band (7-12 GHz) based on technology of gallium nitride (GaN) high electron mobility transistor (HEMT) with a T-gate, which has 100 nm width, on a silicon (Si) semi-insulating substrate of the OMMIC company. The amplifier is based on common-source transistors with series feedback, which was formed by high-impedance transmission line, and with parallel feedback to match noise figure and power gain. The key characteristics of an LNA are noise figure and gain. However, in this paper, it was decided to design the LNA, which should have a good margin in terms of input and output power. As a result, GaN technology was chosen, which has a higher noise figure compared to other technologies, but eliminates the need for an input power limiter, which in turn significantly increases the overall noise figure. As a result LNA MMIC was developed with the following characteristics: noise figure less than 1.6 dB, small-signal gain more than 20 dB, return loss better than -13 dB and output power more than 19 dBm with 1 dB compression in the range from 7 to 12 GHz in dimensions 2x1.5 mm², which has a supply voltage of 8 V and a current consumption of less than 70 mA. However, it should be said that LNA was only modeled in the AWR DE.

An image-reject down-converter for IEEE 802.11a and ETSI HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f T silicon bipolar process. The circuit integrates a variable-gain low noise amplifier and a double-balanced mixer along with passive image rejection filters. It exhibits a 4-dB noise figure and a power gain of 23 dB. By reducing the low noise amplifier gain by 9 dB (thanks to a 1-bit gain control), the down-converter achieves an input 1-dB compression point of ---14 dBm, while drawing only 23 mA from a 3-V supply voltage. The adopted filtering approach provides an image rejection ratio higher than 60 dB.

A cascode bipolar low-noise amplifier (LNA) with capacitive shunt feedback has been developed to present a solution for simultaneous noise and power match when the real part of the optimum source impedance is not 50 Ω in order to keep high current density under power constraint. The proposed LNA also has the capability for the simultaneous improvement of noise figure (NF) and linearity. In addition, we analyzed and verified that the second-order interaction, which affects the third-order nonlinearity, becomes less sensitive to the low-frequency input termination at higher bias currents. The possibility of removing the low-frequency LC trap is investigated based on this analysis. We also show that LNAs with smaller base and/or smaller emitter resistances require lower source impedance at low frequencies to improve linearity by the same amount. Finally, prudent layouts for improving the performance of the LNA are considered. Eleven design examples of the proposed LNA, which individually operate at 880, 1575, or 1960 MHz, are fabricated in a low-cost 0.35- μm SiGe BiCMOS process to verify the design and analysis experimentally. The fabricated LNAs have excellent performances, especially in NF. For example, the 880-MHz LNA has an NF of 0.9 dB, a power gain of 16 dB, and an IIP3 of +14 dBm with current consumption of 11 mA from a 2.8-V power supply.

<p class="Abstract"><span>The demand of low noise amplifier (LNA) has been rising in today’s communication system. LNA is the basic building circuit of the receiver section satellite. The design concept demonstrates the design trade off with NF, gain, power consumption. This paper reports on with analysis of wideband LNA. This paper shows the schematic of LNA by using Darlington pair amplifier. This LNA has been fabricated on 90nm CMOS process. This paper is focused on to make comparison of three stage and single stage LNA. Here, the phase mismatch between these patameters is quantitavely analyzed to study the effect on gain and noise figure (NF). In this paper, single stage LNA has shown the 23 dB measured gain, while the three stages LNA has demonstrated 29 dB measured gain. Here, LNA designed using darlington pair shows low NF of 3.3-4.8 dB, which comparable to other reported single stage LNA designs and appreciably low compared to the three stages LNA. Hence, findings from this paper suggest the use of single stage LNA designed using Darlington pair in transceiver satellite applications.</span></p>

In a radio frequency (RF) transceiver, low noise amplifier (LNA) plays a critical role in determining the receiver performance. This paper elucidates the design of an LNA for optimizing its gain, noise figure and stability factor with different transistor configurations in the frequency range of 5-6 GHz. Design-optimization of LNA has been performed with standard transistor (BJT and MOSFET) files in circuit simulation software. For comparison we have considered the following configurations of LNA: (i) a single stage npn BJT LNA, (ii) npn BJT and NMOS cascode LNA, and (iii) npn BJT and CMOS cascode LNA. Simulation results show that compared to other configurations npn BJT-NMOS cascode LNA depicts the highest gain of 20.42 dB and the lowest noise figure of 0.25. On the other hand, npn BJT-CMOS cascode LNA demonstrates the highest stability factor of 1.07 followed by npn BJT LNA and npn BJT-NMOS cascode LNA configurations respectively. Further improvement in the LNA performance metrics is feasible by parametric optimization of transistor parameters and passive elements in the matching network.

This paper presents the design and simulation of a 60GHz low noise amplifier (LNA) using 40nm CMOS technology for millimeter-waves (MMW) wireless communication applications. A regulated cascode (RGC) topology is adopted to improve the gain and noise performance of the LNA. Simulated results show that the proposed LNA achieves a power gain of 10.4dB and a noise figure (NF) of 5.8dB at 60GHz. The 3dB bandwidth is 6GHz from 56GHz to 62GHz, and the NF is less than 6.4dB across the entire band. The whole circuit consumes 12.2mW with a 1.1V supply. To the author's knowledge, the proposed LNA achieves quite a low power consumption while having such a gain and NF at 60GHz.

The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words. In low noise amplifier (LNA) design, a prominent trade-off usually exist between noise-figure (NF) and gain. In this paper, impact of quality-factor (Q) of the inductors used in LNA design on the overall noise-figure and gain parameters are discussed. To understand the efficacy of the dependency of Q of inductors on NF, LNA with inductor available in UMC 0.18 μm Process Design Kit and LNA with parameterized-cell (pcell) based layout optimized high Q tapered inductors are realized, simulated and compared. Simulations study are carried out on a cascode source degenerated LNA. First, the LNA design is studied for different values of finite Q using library inductors. It is observed that the noise figure is reduced by about 65% (2.66 dB–1.61 dB) and gain is improved by about 30.2% (7.63–9.94) for the same design when Q of the inductors are increased from 10 to 30. Finally, the design is implemented using layout optimized high Q tapered inductors achieving lower noise figure of 1.2 dB with a better gain value of 16.45 and input return loss of −29.31 dB.

PVT-compensated low voltage LNA based on variable current source for low power applications

This paper presents an ultra-wideband (UWB) CMOS low noise amplifier (LNA) that combines a narrowband LNA with resistive shunt- feedback. A new feedback topology is proposed based on the analysis of the influences of feedback scheme on the performances of the LNA. The noise figure (NF) and the power gain, compared with those of a previous shunt-feedback LNA topology, are decreased by 0.8 dB and increased by 2.5 dB respectively while other performances have little change. Designed in a 0.18- mum CMOS technology, the LNA shows a minimum NF of 2.2 dB, a power gain of 11 dB with plusmn0.6 dB variation, and an input return loss of more than 9 dB over the 3.1-5 GHz UWB band.