A comparative study between Class-C and Class-B quadrature voltage-controlled power oscillator for multi-standard applications

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

Low power K-band voltage-controlled oscillator (VCO) using 180nm CMOS technology is presented in this paper. The proposed VCO achieves a wide tuning range from 21.4 to 25.16 GHz by using switched capacitors. The performance of proposed VCO (phase noise, output power and DC power consumption) is improved by designing a new high quality factor inductor that has a shape of figure of eight in 0.18 μm CMOS technology, the quality factor of the proposed inductor is 20.8 at the frequency of interest. Two NMOS switching capacitors to select one of four different frequency. The VCO core consumes 2.7 mA from a power supply of 1.1 V. From the post layout simulation the proposed VCO achieves a wide-frequency tuning range of 21.4–25.16 GHz (16.15%), and a good phase noise of −99 dBc/Hz at 1MHz offset from 25.16 GHz carrier frequency. The calculated figure of merit (FoM) and FoM t of this VCO are −183 dBc/Hz and −187 dBc/Hz.

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core cross-coupled voltage-controlled oscillators (VCOs) using indirect back-gate coupling. In conventional direct-back coupling the resonator's voltage swing, tuning range, and quality factor are respectively limited by the forward-conducting back-gate junction cut-in voltage, diffusion capacitance and small dynamic resistance. To generate quadrature phase signals with strong coupling strength and large output swing, the proposed design uses pMOSFETs as buffers between the back-gate diode and LC tank to eliminate the drawback in existing back gate coupling QVCOs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M technology. At the supply voltage of 0.8 V, the total power consumption is 4.4 mW. The free-running frequency of the QVCO is tuneable from 5.96 GHz to 6.60 GHz as the tuning voltage is varied from 0.0 V to 0.8 V. The measured phase noise at 1 MHz frequency offset is -120.5 dBc/Hz at the oscillation frequency of 6.59 GHz and the figure of merit (FOM) of the proposed QVCO is -190.4 dBc/Hz.

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) coupled via varactors. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm CMOS technology and the die area is 0.61 × 0.95 mm2. At the supply voltage of 1.2 V, the total power consumption is 3.7 mW. The free-running frequency of the QVCO is tunable from 3.86 GHz to 4.22 GHz as the tuning voltage is varied from 0.0 to 1.2 V. The measured phase noise at 1 MHz frequency offset is -123.42 dBc/Hz at the oscillation frequency of 3.94 GHz and the figure of merit (FOM) of the proposed QVCO is -190.38 dBc/Hz.

Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-locked quadrature voltage-controlled oscillator (QVCO) and quadrature frequency-locked loop (FLL) are presented in this paper using 90-nm CMOS process. A modified self-injection technique is employed in the QVCO to reduce quadrature error and phase noise. A transformer coupled topology is adopted to widen the locking range (LR) of the subharmonically injection-locked QVCO. With a subharmonic number of 3, the proposed subharmonically injection-locked QVCO demonstrates an overall LR of 3.5 GHz, a phase noise of −126.8 dBc/Hz at 1-MHz offset, a phase error of 0.32°, and an amplitude error of 0.26 dB. Moreover, the quadrature FLL is developed using the QVCO, and the subharmonic number can be up to 32 since the control voltage of the QVCO is adaptively aligned to overcome the LR. The operation frequency of the subharmonically injection-locked quadrature FLL is from 49 to 51.4 GHz. The measured amplitude and phase errors are 0.5 dB and 2.5°, respectively. Between 15 °C and 50 °C, the measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are lower than −106 dBc/Hz and 110 fs, respectively. Compared to the prior art, the proposed $V$ -band subharmonically injection-locked quadrature QVCO and quadrature FLL feature excellent performance and good robustness.

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of −119.2dBc/Hz at 10MHz offset of a 56.2GHz carrier and a tuning range of 9.1% (FOM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of −179dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10MHz offset among all the QVCOs around 50–60GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76GHz VCO and a 90GHz VCO, both fabricated in a 65nm CMOS process, with an FOM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 173.6dBc/Hz and 173.1dBc/Hz, respectively.

To design a multi standard and a multi band transceiver, a quadrature voltage controlled oscillator (VCO), which has a wide tuning range, is essential, while providing low phase noise with low current consumption. In this paper, a dual band quadrature VCO in 0.18 mum CMOS process is presented. To accomplish dual band operation, reconfigurable LC tank is adopted. Series coupling transistors are attached to generate quadrature phase signal with low power consumption and low phase noise. To improve phase noise performance, current sources are eliminated and a filter inductor at the common source node is added. The measured phase noises of low frequency mode and high frequency mode are -101.81 dBc/Hz and -100.59 dBc/Hz at 10 kHz offset frequency; and -123.83 dBc/Hz and -115.06 dBc/Hz at 1 MHz offset frequency and figure of merit (FoM) at 1 MHz offset frequency of -181.8 dB and -180.5 dB with 4 mA current consumption with a 1.7 V supply.

Integrated multi-band RF transceiver design for multi-standard applications using 130 ​nm CMOS technology

A dual‐band quadrature voltage‐controlled oscillator (QVCO) with high figure‐of‐merits (FOMs) and cost‐area efficiency is presented by integrating with differential inner‐diamond‐structure switchable inductors which have improved performances. This proposed QVCO is fabricated in a 0.18‐μm complementary metal‐oxide semiconductor process with an active‐region area of 0.61 mm 2 . The QVCO core totally consumes 6.8 mA from 1.8 V supply voltage. The frequency tuning ranges are 120 MHz (from 3.18 to 3.3 GHz) for the low‐band and 500 MHz (from 6.94 to 7.44 GHz) for the high‐band, while the tuning voltage rises from 0 to 1.8 V. The best phase noises with an offset frequency of 1 MHz from the oscillation frequency in the low‐ and high‐bands are −121.9 and −117.5 dBc/Hz, respectively. The measured phase errors in both high‐band and low‐band are less than 1°. The calculated FOMs, no matter the switch is off or on, are better than −180 dBc/Hz.

A trifilar-transformer-coupling quadrature voltage-controlled oscillator (TTC-QVCO) with dual transformer-feedback technology is proposed. Compared to traditional QVCOs, the proposed TTC-QVCO provides an additional coupling path, and therefore achieves an improved quadrature phase accuracy, a lower phase noise and a wider tuning range. The TTC-QVCO, implemented in a 0.18-μm CMOS technology, exhibits a frequency tuning range of 19.6% centered at 5.4 GHz and a power consumption of 5.4 mW from a 1.35 V supply voltage. The QVCO has a measured phase noise of -120.42 dBc/Hz at 1-MHz offset and quadrature phase error of less than 2° with a FoMT of 194.3 dB.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

This article presents a new fully‐integrated quadrature voltage‐controlled oscillator (QVCO), which consists of two differential VCOs coupled via an inductor‐ring. The proposed CMOS QVCO has been implemented with the TSMC 0.18‐μm CMOS technology and the die area is 0.693 × 0.976 mm 2 . At the supply voltage of 0.7 V, the total power consumption is 2.58 mW. The free‐running frequency of the QVCO is tunable from 5.15 to 5.55 GHz as the tuning voltage is varied from 0 to 0.7 V. The measured phase noise at 1 MHz frequency offset is −120.88 dBc/Hz at the oscillation frequency of 5.28 GHz and the figure of merit of the proposed QVCO is −191.21 dBc/Hz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:310–313, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27283

Since the conventional figure of merit (FOM) neglects the flicker-noise effect in a voltage-controlled oscillator (VCO), we devised a new FOM that considers the flicker-noise effect and, thus, allows phase noise (which is dominated by flicker noise) of different VCOs to be compared. Using the proposed FOM, we analyze the phase noise and power dissipation in an inverter-based ring oscillator, since it has a simple topology and few noise sources. From this analysis, we draw three conclusions: first, varying load capacitance changes oscillation frequency only without changing proposed FOM; second, to improve the proposed FOM, large transistor length should be chosen, third, comparing FOM of a VCO and FOM calculated from target specifications of phase noise and power dissipation shows that the designed VCO meets target specifications. This second and third conclusion is useful for easily designing an actual inverter-based quadrature-ring VCO. A prototype inverter-based quadrature-ring VCO was fabricated by using 0.18-μm CMOS technology with an active die area of 0.018 mm2. It consumes 2.61 mW from a 1.8-V power supply. Moreover, it has an oscillation frequency of 338.5 MHz, phase noise of -110 dBc/Hz at 1-MHz offset frequency, and proposed FOM of 160.4 dB (at 0.1-MHz offset frequency).