CMOS Quadrature VCOs Using the Varactor Coupling Technique

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core cross-coupled voltage-controlled oscillators (VCOs) using indirect back-gate coupling. In conventional direct-back coupling the resonator's voltage swing, tuning range, and quality factor are respectively limited by the forward-conducting back-gate junction cut-in voltage, diffusion capacitance and small dynamic resistance. To generate quadrature phase signals with strong coupling strength and large output swing, the proposed design uses pMOSFETs as buffers between the back-gate diode and LC tank to eliminate the drawback in existing back gate coupling QVCOs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M technology. At the supply voltage of 0.8 V, the total power consumption is 4.4 mW. The free-running frequency of the QVCO is tuneable from 5.96 GHz to 6.60 GHz as the tuning voltage is varied from 0.0 V to 0.8 V. The measured phase noise at 1 MHz frequency offset is -120.5 dBc/Hz at the oscillation frequency of 6.59 GHz and the figure of merit (FOM) of the proposed QVCO is -190.4 dBc/Hz.

This article presents a new fully‐integrated quadrature voltage‐controlled oscillator (QVCO), which consists of two differential VCOs coupled via an inductor‐ring. The proposed CMOS QVCO has been implemented with the TSMC 0.18‐μm CMOS technology and the die area is 0.693 × 0.976 mm 2 . At the supply voltage of 0.7 V, the total power consumption is 2.58 mW. The free‐running frequency of the QVCO is tunable from 5.15 to 5.55 GHz as the tuning voltage is varied from 0 to 0.7 V. The measured phase noise at 1 MHz frequency offset is −120.88 dBc/Hz at the oscillation frequency of 5.28 GHz and the figure of merit of the proposed QVCO is −191.21 dBc/Hz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:310–313, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27283

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a-b-g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross-coupled LC VCOs to generate in-phase (I) and quadrature (Q) signals operating at one-thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single-stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is −104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm2 on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.

To design a multi standard and a multi band transceiver, a quadrature voltage controlled oscillator (VCO), which has a wide tuning range, is essential, while providing low phase noise with low current consumption. In this paper, a dual band quadrature VCO in 0.18 mum CMOS process is presented. To accomplish dual band operation, reconfigurable LC tank is adopted. Series coupling transistors are attached to generate quadrature phase signal with low power consumption and low phase noise. To improve phase noise performance, current sources are eliminated and a filter inductor at the common source node is added. The measured phase noises of low frequency mode and high frequency mode are -101.81 dBc/Hz and -100.59 dBc/Hz at 10 kHz offset frequency; and -123.83 dBc/Hz and -115.06 dBc/Hz at 1 MHz offset frequency and figure of merit (FoM) at 1 MHz offset frequency of -181.8 dB and -180.5 dB with 4 mA current consumption with a 1.7 V supply.

A comparative study between Class-C and Class-B quadrature voltage-controlled power oscillator for multi-standard applications

Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-locked quadrature voltage-controlled oscillator (QVCO) and quadrature frequency-locked loop (FLL) are presented in this paper using 90-nm CMOS process. A modified self-injection technique is employed in the QVCO to reduce quadrature error and phase noise. A transformer coupled topology is adopted to widen the locking range (LR) of the subharmonically injection-locked QVCO. With a subharmonic number of 3, the proposed subharmonically injection-locked QVCO demonstrates an overall LR of 3.5 GHz, a phase noise of −126.8 dBc/Hz at 1-MHz offset, a phase error of 0.32°, and an amplitude error of 0.26 dB. Moreover, the quadrature FLL is developed using the QVCO, and the subharmonic number can be up to 32 since the control voltage of the QVCO is adaptively aligned to overcome the LR. The operation frequency of the subharmonically injection-locked quadrature FLL is from 49 to 51.4 GHz. The measured amplitude and phase errors are 0.5 dB and 2.5°, respectively. Between 15 °C and 50 °C, the measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are lower than −106 dBc/Hz and 110 fs, respectively. Compared to the prior art, the proposed $V$ -band subharmonically injection-locked quadrature QVCO and quadrature FLL feature excellent performance and good robustness.

ABSTRACTThis letter presents a 2.1 GHz Class‐C quadrature voltage‐controlled oscillator (QVCO) working on coupling two identical Class‐C VCOs. The class‐C oscillator is used to achieve the performance of low phase noise. The QVCO uses a varactor ring to generate quadrature phase and it was implemented using the TSMC 0.18 μm CMOS 1P6M process. The output phase noise of the QVCO is −130.34 dBc/Hz at 1 MHz offset frequency from the output carrier frequency of 1.978 GHz; the quadrature phase error is 0.33° and the figure of merit is −190.61 dBc/Hz. Total power consumption is 3.9 mW. Tuning range is about 422 MHz (19%) between 1.978 and 2.4 GHz, while the control voltage was tuned from 0 V to 2 V. The die area is 0.528 × 1.168 mm2. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1961–1964, 2016

This paper presents a fully integrated 1.8 GHz, 0.35-mum CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range

A dual‐band quadrature voltage‐controlled oscillator (QVCO) with high figure‐of‐merits (FOMs) and cost‐area efficiency is presented by integrating with differential inner‐diamond‐structure switchable inductors which have improved performances. This proposed QVCO is fabricated in a 0.18‐μm complementary metal‐oxide semiconductor process with an active‐region area of 0.61 mm 2 . The QVCO core totally consumes 6.8 mA from 1.8 V supply voltage. The frequency tuning ranges are 120 MHz (from 3.18 to 3.3 GHz) for the low‐band and 500 MHz (from 6.94 to 7.44 GHz) for the high‐band, while the tuning voltage rises from 0 to 1.8 V. The best phase noises with an offset frequency of 1 MHz from the oscillation frequency in the low‐ and high‐bands are −121.9 and −117.5 dBc/Hz, respectively. The measured phase errors in both high‐band and low‐band are less than 1°. The calculated FOMs, no matter the switch is off or on, are better than −180 dBc/Hz.

This paper presents a fast and autonomous injection frequency tracking and locking technique. In the present injection-locking system, a quadrature injection-locked oscillator (QILO) is third harmonically locked to a quadrature voltage-controlled oscillator (QVCO). In the frequency tracking loop, the frequency difference between QVCO and QILO is extracted using the QILO's amplitude modulated (AM) envelope waveform. The AM frequency of the envelope signal bears frequency difference between the two oscillators. The envelope signal is further converted to pulse signal which subsequently drives digital feedback control circuitry to update the QILO's output frequency so that it can track the third harmonic of the injection QVCO. The frequency calibration process is purely autonomous, self-initiating whenever the AM modulated envelope waveform is generated. The feedback signal is primarily processed in the digital domain, resulting in a compact, fast, and power-efficient injection frequency-locked loop (IFLL). By incorporating a phase noise (PN) calibration routine after completing the frequency calibration, the presented IFLL resolves the intractable issue of PN degradation at the edge of the slave oscillator's injection locking range. This results in a large injection frequency tracking range of 26.5-29.7 GHz which is only limited by the QILO's LC tank tuning range. The IFLL realized in 0.13-μm CMOS consumes 2.4 mW with a negligible area penalty. Overall chip size including QVCO, QILO, and IFLL is 1 × 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The first fully integrated GaInP/GaAs heterojunction bipolar transistor (HBT) quadrature voltage controlled oscillator (VCO) using the stacked-transformer LC tank is demonstrated at 5.43–5.31 GHz with low-phase-noise performance. The stacked-transformers are formed by two interconnect metal layers and possess good electrical properties at high frequencies because of the semi-insulating GaAs substrate. The quadrature VCO at 5.38 GHz has phase noise of −127.4 dBc/Hz at 1 MHz offset frequency, output power of −4 dBm and a figure of merit (FOM) −191 dBc/Hz.

A high performance X-band quadrature voltage-controlled oscillator (QVCO) is presented. The transformer feedback topology is proposed to combine with the interactive self-switching current bias technique, which can achieve a low phase noise while maintaining low power consumption simultaneously. The measured phase noise is −123.84 dBc/Hz at 1-MHz offset with a 10.56 GHz carrier frequency and the IQ phase error is less than 1.9°. Under a power consumption of 2.4 mW, the proposed QVCO in 0.18- $ {\mu }\text{m}$ CMOS achieves an excellent FoM up to −200.5 dBc/Hz, which is among the best compared with previous works using a similar technology.