A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability

By analyzing the principle of process variations, a lightweight Physical Unclonable Function (PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation (SMIC) 65 nm CMOS technology and the layout area is 2.94 μm × 1.68 μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO's to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.

Physical Unclonable Functions (PUFs) are promising security primitives for resource-constrained network nodes. The XOR Arbiter PUF (XOR PUF or XPUF) is an intensively studied PUF invented to improve the security of the Arbiter PUF, probably the most lightweight delay-based PUF. Recently, highly powerful machine learning attack methods were discovered and were able to easily break large-sized XPUFs, which were highly secure against earlier machine learning attack methods. Component-differentially-challenged XPUFs (CDC-XPUFs) are XPUFs with different component PUFs receiving different challenges. Studies showed they were much more secure against machine learning attacks than the conventional XPUFs, whose component PUFs receive the same challenge. But these studies were all based on earlier machine learning attack methods, and hence it is not clear if CDC-XPUFs can remain secure under the recently discovered powerful attack methods. In this paper, the two current most powerful two machine learning methods for attacking XPUFs are adapted by fine-tuning the parameters of the two methods for CDCXPUFs. Attack experiments using both simulated PUF data and silicon data generated from PUFs implemented on field-programmable gate array (FPGA) were carried out, and the experimental results showed that some previously secure CDC-XPUFs of certain circuit parameter values are no longer secure under the adapted new attack methods, while many more CDC-XPUFs of other circuit parameter values remain secure. Thus, our experimental attack study has re-defined the boundary between the secure region and the insecure region of the PUF circuit parameter space, providing PUF manufacturers and IoT security application developers with valuable information in choosing PUFs with secure parameter values.

A Physical Unclonable Function (PUF) is a die specific random function that can be used in a number of secure IC applications including die identification/authentication and key generation. At the core of a silicon PUF is a circuit (the PUF core) that generates random bits. These bits are like a silicon biometric, unique across dies, but can be reliably reproduced multiple times on a die across voltage and temperature variations and aging. In this thesis, we discuss various aspects of a PUF design, with a strong focus on circuit details. We describe the properties and the figures of merit of a PUF and then compare various PUF core implementations. We identify the biggest design challenges and provide several solutions. Results in this work are supported by measurement data from testchips designed in 65nm bulk CMOS. We provide an apples-to-apples comparison of various PUF implementations. We demonstrate that while adequate randomness and uniqueness is achievable for most PUF implementations, achieving high reliability is a challenge. The conventional method to achieve high reliability is to use error correcting codes (ECC). Unfortunately, the overheads associated with these techniques grows very quickly with error correction capability. Alternately, researchers have proposed several error reduction techniques to minimize the use of error correction. In this work, we evaluate four orthogonal and complementary error reduction techniques. Two of these techniques, categorized as extrinsic techniques, are multiple evaluation (ME) and activation control (AC) and are able to reduce errors in PUF response by ~70-80%. The other two techniques, categorized as intrinsic, are post-silicon selection (PSS) and directed accelerated aging (DAA) and show ~100% correction of errors. As a proof of concept prototype, we describe a self-contained, BIST-controlled key-generator that implements the PSS technique to autonomously generate bits with a bit error rate < 5 * 10^-9, equivalent to a 128-bit key error rate < 10^-6. We also describe a realization of a strong-PUF that uses these highly reliable bits in conjunction with an Advanced Encryption Standard (AES) primitive.

Embedded systems carry and process more and more sensitive information in untrusted environments, where an attacker can wiretap the external communication and also has unlimited physical access to the device. Cryptography protects systems against many of the threats and relies on the security of the cryptographic keys inside the system. Physical Unclonable Functions (PUFs) measure manufacturing variations inside integrated circuits, for example FPGAs, to generate a unique secret PUF response inside each device. Similar to deriving a biometric pattern from human features, the individual pattern inside an FPGA differs slightly from measurement to measurement. From these measurements, the PUF response is generated to derive a secure and reliable cryptographic key. The Ring-Oscillator (RO) PUF is a popular PUF type because of its high randomness and reliability. Frequencies of ROs are compared pairwise to derive one secret bit. So far, the reliability of RO PUFs was evaluated by counting bit flips in measured PUF responses. This work analyzes the distribution of frequency measurements to derive the behavior of the PUF. Analyzing the frequency distributions gives a more precise estimation of the PUF bit error rates than measuring the bit errors after the comparison of two oscillator frequencies. The evaluation of publicly available real world empirical FPGA data has shown that most error probabilities of RO PUF responses are so low that they cannot be measured in feasible time. For almost 200 evaluated FPGAs, more than 70% of the PUF outputs on every FPGA have bit error probabilities under 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> . We can even ensure this error probability for over 60% of the PUF outputs after a practicable number of frequency measurements with a confidence of 99.9%. Index Terms-Physical Unclonable Functions (PUFs), Ring Oscillator PUF, FPGA, Statistics.

Emerging physical unclonable function (PUF) circuit designs in the IC supply chain pose not only a challenge to security threats but also a serious concern about hardware efficiency. The existing conventional PUF methods extract intrinsic random physical variation to generate two-valued secret key bits, which lack logical complexity and have poor efficiency in interconnect lines. This paper proposes a multiple-valued logic PUF circuit (MPUF), which focuses on adding logical complexity and minimizing hardware cost by processing on multilevel-cell and interconnect lines. The twins' cell is selected as the MPUF cell to source the multiple-valued physical variation, and the bit-line sharing strategy was integrated to implement the four-valued PUF data. After full-custom designing, the MPUF with 512 cells only needs 16 transmit bit lines. The proposed MPUF chip is fabricated under 65-nm CMOS technology and the core area occupies approximately 0.016 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a 4.9-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> bitcell size. The measured results show that the MPUF data passed National Institute of Standards and Technology randomness tests, and that it operates 0.1-pJ/b energy efficiency at 1.2 V, ensures randomness and uniqueness with 50.42% hamming distance, and less than 0.04 autocorrelation at 95% confidence level. Compared with other state of the arts, logical complexity improves 50% for resisting power attacks.

Physically unclonable functions (PUFs) have drawn attention as one of the key security primitives for IoT devices since they can provide unique, random, stable, and unclonable hardware fingerprints, ie. keys, for secure authentication. Numerous PUF designs have been evolved to provide stable keys at a lower cost, ie. with small area. Early SRAM-based PUFs [1, 2] had large area $(\gt9,000{\mathrm {F^{2}/bit}})$ and was unstable with a native BER of 8.3*. Various stabilization techniques were proposed such as temporal majority voting (TMV), burn-in, and dark bit masking, at the cost of large additional peripheral circuits and significant loss of challenge-response-pairs (CRPs). But resulting BER was still very high ($\sim$ 1*) even with 8.6x BER improvement. An inverting logic gate cell-based PUF with high reliability [3] and synthesizable PUF [4] were also proposed but the large area (5,057F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit,2,686F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit) limited cost efficiency. A 2-T amplifer-based PUF achieved 553-782F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit area [5, 6] but the initial version had a high BER due to the lack of a stabilization method [5]. Therefore, in the following work [6], a stabilization method was subsequently proposed and BER could be significantly improved. A leakage-based PUF with a lossless stabilization method called ‘remapping’ was proposed in [7], which allowed stabilization without sacrificing CRPs as required in [1–3, 6]. To further improve cost efficiency, a PUF with a differential NAND structure [8] was proposed with an extremely small area of $20{\mathrm {F^{2}/bit}}$. However, there was no means of stabilization applicable, other than TMV, making it unstable and susceptible to voltage or temperature (V/T) variations. Therefore, in this paper, a current-integrated differential NAND-structured PUF (CI NAND-PUF) is proposed, where stabilization methods other than TMV is made applicable. By applying trimming and remapping, up to 12.8x stability improvement is achieved with extremely cost-efficient PUF with 20F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit area, while also significantly reducing peripheral circuit overhead on [8].

Modern embedded electronic devices are gradually becoming an essential part of everyday lives, proving indispensable for daily activities. The growth of the Internet of things (IoT) technology fuels this phenomenon. IoT devices are found everywhere around us – smartphones, smartwatches, home automation, autonomous cars, and medical implants for human bodies. These devices find widespread use in medical imaging, video surveillance as embedded vision, cloud computing platforms, and military applications. Ensuring the reliability and safety of these devices is of prime importance, since these devices store sensitive data. A wide range of such embedded devices is a common target for intellectual property (IP) theft and reverse-engineering attacks by hackers to access confidential information and counterfeit integrated circuits. Physically unclonable functions (PUFs) are innovative hardware defense techniques that promise a fundamental change in our approach to many security problems. PUFs possess desirable properties like low cost, simple architectures, a light weight, versatility, and the valuable advantage of unclonability. This unclonable property is a consequence of intrinsic random variations at the micro- and nanoscale levels in the manufacturing processes and cannot be controlled or removed. This characteristic also serves as a unique fingerprint for the integrated circuit chips, similar to humans. The widespread usage of PUF techniques in security applications makes it imperative for hardware designers to appreciate its working and understand its uses in practice fully. This chapter aims to address these and other topics by presenting a detailed introduction of the concepts, evaluation parameters, and various ramifications of physically unclonable functions. PUF techniques also provide an economical alternative to ciphers and hash functions for secure cryptographic protocols. It is also necessary to provide security of IoT devices, have economic viability, and fit well with embedded devices’ heterogeneous nature. PUF circuits receive challenges as a sequence of bits and generate matching responses called a challenge-response pair, which can be thought of as a secret key or unique fingerprint. It also obviates the need for storing the keys in nonvolatile memories with dedicated protection, which is a costly affair. In this chapter, different PUFs, including optical PUF, delay-based PUFs, weak and strong PUFs, etc., the maturity of this technology, and their various applications are investigated. This chapter also emphasizes critical challenges toward PUF utilization in IoT and related fields and significant future development areas like critical public infrastructure, reconfigurability, and bit-specific reliability. The unique IoT domain protection criteria and how PUFs can be used to fulfill them are also examined. The chapter’s emphasis is on proven and well-understood strategies involving their benefits and shortcomings.

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

In this paper, a coded modulation scheme employing signal shaping is proposed and designed for use in multi-valued physical unclonable functions (PUFs). In the literature, usually binary PUFs are considered, where less than one bit of entropy is extracted from each fundamental building block (PUF node). This randomness in the hardware may then be used for the derivation of cryptographic keys. Meanwhile, PUFs over higher-order alphabets, so-called multi-valued PUFs (MVPUFs) have been presented. Typically, symbols from a higher-order alphabet are extracted by suited quantization. In contrast, in this paper we propose a coded modulation scheme which directly works on the analog values provided by the PUF nodes. We establish an interpretation as digital transmission with randomness at the transmitter, and thereon calculate the respective capacities of bit levels for the Gaussian distributed reference PUF readout in additive Gaussian noise. In addition, the metric for optimum soft-decision decoding is derived. Thereby, the coded modulation scheme can be designed for the present situation. A helper data scheme adapted to the given situation is proposed and analyzed. Moreover, on top of the multilevel coding scheme, we employ signal shaping for the first time in the context of PUFs. In particular, trellis shaping is applied. By this, the coded modulation scheme can be perfectly matched to the PUF statistics. This is reflected by the results of conducted numerical simulations. High coding rates can be used, i.e., a large entropy per PUF node can be extracted, with very high reliabilities.

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive random access memory (RRAM)-based PUF chip with 8-kb capacity is developed. Two operation modes, namely differential mode and median mode, are embedded on chip. To implement these modes, a current sampling-based sense amplifier is designed to distinguish the current values of the PUF cells and the reference cell. In addition, a split-resistance scheme is proposed to enhance the PUF's reliability significantly. The experiment results show that the differential PUF exhibits excellent performance with native bit error rate (N-BER) below 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> and inter-Hamming distance (inter-HD) of 49.99%. In the meanwhile, the reconfigurability of PUF challenge-response pairs (CRPs) is demonstrated with 49.77% and 47.29% reconfigure-Hamming distance (reconfigure-HD) in the median mode and the differential mode, respectively.

Hardware Trojan has emerged as a major security concern for integrated circuits. This paper presents a novel design obfuscation scheme against hardware Trojan attacks based on chaos finite state machine (FSM) and delay chains array physical unclonable function (PUF). We exploits the pseudo-random characteristics of the M-sequences to propose a chaos FSM design method which can generate exponentially many random states and transitions to obfuscate the chip’s functional states with low overhead. The chip’s functionalities are locked and obfuscated and would not be functional without a unique key that can only be computed by the designer. We also propose a new PUF construction method, named delay chains array PUF (DAPUF), to extract the unique power-up state for each chip which is corresponding to a unique key sequence. We introduce confusions between delay chains to achieve avalanche effects of the PUF outputs. Thus the proposed DAPUF approach can provide large number of PUF instances with high accuracy and reverse-engineering resistant. Through the proposed obfuscation scheme, the designer can control the IC’s operation modes (chaos mode and normal mode) and functionalities, and can also remotely disable the chips when hardware Trojan insertion is revealed. The functional obfuscation prevents the adversary from understanding the real functionalities of the circuit as well as the real rare events in the internal nodes, thus making it difficult for the adversary to insert hard-to-detect Trojans. It also makes the inserted Trojans become invalid since the Trojans are most likely inserted in the chaos mode and will be activated only in the chaos mode. Both simulation experiments on benchmark circuits and hardware evaluations on FPGA show the security, low overhead and practicality of the proposed method.

Physical Unclonable Function (PUF) is recently used in modern electronic systems for device authentication and secret key generation. SRAM PUF is a popular memory-based PUF because it is a standard component for most electronic devices. Previously only strongly stable RAM bits are selected as PUF bits in order to achieve high reliability, hence requiring relatively large SRAM. Furthermore, SRAM PUF might suffer from PUF clone attack for using stable bits. Attackers may use Photon Emission Analysis (PEA) to observe the behavior of the stable bits and conducted Focused Ion Beam circuit edit (FIBCE) to produce an identical physical response. In this paper, we propose a new method that employs unstable bits as PUF bits in addition to the stable bits to increase the SRAM bit usage rate. We also show that this method can efficiently resist the PUF clone attack. Experimental results show that even though our proposed method uses unstable bits as PUF bits, it can still achieve high reliability. It can reach an average 2% intra-HD without Error Correction Code (ECC) under various conditions and an average inter-HD of 49.33%.

A low-density parity check (LDPC) circuit and its properties as a post-processor is proposed for physically unclonable functions (PUFs) applications. PUFs can be realized using process variations or signal noises in SRAM or other PUF circuits, whereas the generated data needs to be processed by error check and correction (ECC) because of their inherent intra-PUF variabilities. The bit-flip LDPC circuits that have been developed in this study reveal compact constructions as well as notable noise tolerances during the ECC calculations. Unlike conventional deterministic post-processing, the LDPC circuits made even under unreliable fabrication conditions keep capable of guaranteeing robustness against noises.