A constant time algorithm for finding maxima on reconfigurable bus systems using fewer processors

Presents an efficient improvement of processor complexity while solving some connectivity problems in processor arrays with reconfigurable bus systems. We first derive two constant time algorithms in the proposed parallel processing system for computing the dominators and the dominator tree of an undirected graph either using a 9-D n/spl times/n/spl times/n processors or a 2-D n/sup 2//spl times/n/sup 2/ processors, where n is the number of vertices of the graph. Then based on the dominator tree algorithm, we also solve many other graph connectivity problems in constant time. They are the articulation points, bridges, biconnected components, and bridge-connected components problems in undirected graphs.

Constant time sorting on a processor array with a reconfigurable bus system

In this paper, we give efficient parallel and distributed algorithms for the topological sort problem on acyclic graphs with n vertices. Our parallel algorithm solves the problem on a CREW PRAM in O(log/sup 2/ n) time with O(M(n)/log n) processors, where M(n) denotes the number of processors needed to multiply two n/spl times/n integer matrices over the integer ring. The best known upper bound of M(n) is O(n/sup 2.376/). The parallel algorithm can also solve the problem on processor arrays with reconfigurable bus systems in O(1) time and O(n/sup 3/) processors. Our distributed algorithm solves the topological sort problem of an arbitrary asynchronous network with communication complexity O(n/sup 2/).

The reconfigurable mesh is a processor array that consists processors arranged in 1-dimensional or 2- dimensional grids with a reconfigurable bus system. The main contribution of this paper is to show initialization algorithms on the 1-dimensional reconfigurable mesh with n processors. We assume that processors are identical, and does not have unique IDs. Initialization is a task that assigns sequential IDs to processors in the reconfigurable mesh. We first show a simple deterministic initialization algorithm for the I-dimensional reconfigurable mesh that runs in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (n) time. This deterministic algorithm is optimal, because no deterministic solution can perform initialization in less than <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (n) time. Quite surprisingly, we show that expected sublinear-time initialization is possible if we use randomized techniques. Our initialization algorithm runs in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ((log n + log f) log log n) time with probability at least 1-1/4 for every real number f ges 1. It follows that the initialization algorithm runs in expected O(log n log log n) time. We also proved that any randomized initialization need to run in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (log n) time. Thus, our randomized initialization algorithm running in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (log n log log n) time is very close to a theoretical lower bound Omega(log n) time.

In this paper, we present an efficient deterministic algorithm for sorting on the LARPBS (Linear Array with a Reconfigurable Pipelined Optical Bus System) model. Our sorting algorithm sorts n general keys in O(logn) time on a LARPBS of size nslogn. The previous best results can sort n items in O(lognloglogn) worst-case time using n processors or sort n items in O((log logn2)worst-case time using n1+ processors. Our algorithm is also scalable to certain extent. When the system size is reduced to nslogn/r for l≤r≤logn, the total computation time is O(rlogn).

A mesh-connected computer enhanced by a reconfigurable bus system is referred to as a reconfigurable mesh (RM). Given an n×n grey-scale image and m×m template, in this paper, an O( log m) time parallel algorithm for template matching is presented on a RM with O(m2n2) processors. Suppose the image and template are binary, an O(1) time algorithm is presented on a RM with O(m3n2) processors. Both algorithms are superior to the best known algorithms on RMs.

A reconfigurable system is a system which may allow the service continuity under failure, on the basis of a reduced level of functionality. In such a system, when one component fails the rest of the system keeps working with some acceptable performance degradation. To distinguish between the normal behavior and the degraded one, the production rate is used as a performance measure. Two optimization problems dealing with reconfigurable systems are addressed. We consider a series system consisting of N stochastically independent components. Different technologies are assumed to be available for each component. The following design problems are studied: (i) Find the configuration which allows maximizing the production rate of the system under resource constraints. (ii) Find the configuration that allows to reach some predetermined level of production rate at minimal cost.

Reconfigurable systems are the safe dynamical systems wherein the health of the control input and/or sensor output variables are continuously monitored and then they are reconfigured, if necessary, in an event of an unexpected fault detected online. This idea is applied, in particular, at the reconfigurable system where the number of control variables is more than the state variables considered to define its motion. In this paper, an adaptive pole placing controller is developed for use in such reconfigurable systems. Adaptive pole placing controller, in theory, is adaptive to take a fault size and retain the closed loop poles it assigns at fixed locations in the open left half plane of the complex plane. As a result, when the controller is not adaptive, it means that the pole perturbations could lead to catastrophes. However, to design adaptive pole placing controller for a reconfigurable system, fault size is required. Hence, the primary objective of the paper is to present a simple procedure that determines the fault size for tuning in the adaptive pole placing controller. Both direct and full-order Luenberger observer based state feedback adaptive pole placing controllers are presented. In situations where the adaptive pole placing controller is not possible, the fault size for which the reconfigurable system with a non-adaptive pole placing controller would transit from a stable to unstable system (referred as fault tolerant margin with respect to the non-adaptive pole placing controller) is also presented. Some of these features of this paper are illustrated by using the reconfigurable aircraft model available in the literature.

Reconfiguration for seamless mobility has been identified as a key feature of mobile communications beyond 3G. The reconfigurable system in general comprises users, terminals, various radio access schemes, network operators and service providers. A means is required for capturing key stakeholder attributes and also a method for securely sharing those attributes to allow reconfiguration decisions to be made fairly. Identifying a complete list of beneficiaries and their responsibilities and levels of authority within the reconfigurable system will be a major step forward for resolving various issues arising towards the development of this system including the need for standardization, regulation and overall security architecture. This paper introduces new components within the reconfigurable system aimed at addressing these issues, and proposes a preliminary architecture enabling the exchange of profile data between different networks without compromising their security (privacy, integrity, etc).

A vector A of length N can be approximately represented by a histogram H, by writing [0, N) as the non-overlapping union of B intervals I j , assigning a value b j to I j , and approximating A i by H i = b j for i ∈ I j. An optimal histogram representation H opt consists of the choices of I j and b j that minimize the sum-square-error ∥A − H∥ 22 = ∑i | A i − H i |2. Numerous applications in statistics, signal processing and databases rely on histograms; typically B is (significantly) smaller than N and, hence, representing A by H yields substantial compression. We give a deterministic algorithm that approximates H opt and outputs a histogram H such that ∥A−H∥ 22 ≤(l + ε)∥A−H opt∥ 22 . Our algorithm considers the data items A 0, A 1,... in order, i.e., in one pass, spends processing time O(1) per item, uses total space B poly(log(N), log ∥A∥, 1/ε), and determines the histogram in time poly((B, log(N), log ∥A∥, 1/ε). Our algorithm is suitable to emerging applications where signal is presented in a stream, size of the signal is very large, and one must construct the histogram using significantly smaller space than the signal size. In particular, our algorithm is suited to high performance needs where the per-item processing time must be minimized. Previous algorithms either used large space, i.e., Ω(N), or worked longer, i.e., N logΩ(1)(N) total time over the N data items. Our algorithm is the first that simultaneously uses small space as well as runs fast, taking O(1) worst case time for per-item processing. In addition, our algorithm is quite simple.KeywordsHistogramsstreaming algorithms

FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of hardware functions to be configured typically exceeds the underlying chip area during the execution of an application, previous efforts have introduced configuration caching. Those efforts, however, have focused on two run-time-reconfiguration scenarios, which consider a single application running on the reconfigurable system. In the full reconfiguration scenario, functions of an application are arranged into blocks each of which has enough functions to fill the entire chip. The blocks are configured in a deterministic sequence needed by the application based on the a priori knowledge about the application. In the partial reconfiguration scenario, each function is configured or replaced on a function-by-function basis, based on the application needs. In the former technique, spatial processing locality is well exploited. In the latter, only temporal processing locality is exploited. In this work, we propose a technique suitable for multitasking and for cases of single applications that can change the course of processing in a non-deterministic fashion based on data. In order to exploit processing locality, both spatial and temporal simultaneously, the proposed model groups hardware functions into hardware configuration blocks (pages) of fixed size, where multiple pages can be configured on a chip simultaneously. By grouping only related functions that are typically requested together, processing spatial locality can be exploited. Temporal locality is exploited through page replacement techniques. Data mining techniques were used to group related functions into pages. Standard, replacement algorithms as those found in caching were considered. Simulations, as well as emulation using the Cray XD1 reconfigurable high-performance computer were used in the experimental study. The results show a significant improvement in performance using the proposed paging technique.

In this paper we provide a detailed description of a Field Programmable Gate Array (FPGA) based reconfigurable system which has been used in the development of a System on a Chip (SoC) processor and corresponding applications targeted for network computing appliances. The complexity of the processor, in terms of number of hardware threads (64), integrated on chip accelerators and network interfaces, combined with time to market requirements of the final system necessitated hardware verification and software development on pre-silicon systems that provided a high degree of architecture fidelity, reasonable time to completion for verification tests, and sufficient diagnosis tools for root cause analysis from processor logic to application design. To meet these requirements, we developed an FPGA based emulator which actually implemented the combined chip logic function by mapping it to FPGA equivalent gate functions. This system has the advantage over other simulation environments in that it has actual chip logic that can be executed at real world speeds e.g. MHz, rather than the traditional HDL simulators which are typically executed at 10 or 100's of KHz. Additional flexibility in terms of system verification, analysis and application development was provided by the development of a library OS based programming environment, Bare Metal Application (BMA), complimentary to both the FPGA based system as well as the actual silicon. The main contribution of this work was the development of a reconfigurable and flexible simulation system, both hardware and software which, to the best of our knowledge, provided the first heterogeneous multipurpose environment for silicon and software validation on a system with both general purpose cores and on board accelerators.

Dynamically reconfigurable systems have the potential of realising efficient systems as well as providing adaptability to changing system requirements. Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate in dynamic application and communication environments. We propose an approach in which reconfiguration is applied dynamically at various levels of a mobile system, whereas traditionally, reconfigurable systems mainly focus at the gate level only. The research performed in the CHAMELEON project 1 aims at designing such a heterogeneous reconfigurable mobile system. The two main motivations for the system are 1) to have an energy-efficient system, while 2) achieving an adequate Quality of Service for applications.

The optical bus based arrays have recently shown many applications. In this paper we use the pipelining ability of the LARPBS to solve the repetitions detection problem. We propose an algorithm that finds all kind of repetitions in a string including k-power repetitions, overlapping repetitions and non-contiguous repetitions. For a given distance, this operation is performed in O(1) communication cycle with a constant computation time processors on a O(n) processors LARPBS for a string of length n. For all the periods, it is O(n) bus cycle. No previous algorithms were known for this problem on the LARPBS.

Abstract—FPGA-based reconfigurable systems allow the on-line adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA’s reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural on-line test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the perfor-mance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application. Keywords-FPGA, Reconfigurable Architectures, Online Test