Faster Sorting on a Linear Array with a Reconfigurable Pipelined Bus System

We present a fast algorithm for sorting on a linear array with a reconfigurable pipelined bus system (LARPBS), one of the recently proposed parallel architectures based on optical buses. Our algorithm sorts N numbers in O(log N log logN) worst-case time using N processors. To our knowledge, the previous best sorting algorithm on this architecture has a running time of O(log2N).KeywordsLinear ArrayRecursive CallSorting AlgorithmMerging AlgorithmDestination ProcessorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

We present two fast algorithms for sorting on a linear array with a reconfigurable pipelined bus system (LARPBS), one of the recently proposed parallel architectures based on optical buses. In our first algorithm, we sort N numbers in O(log N log log N) worst-case time using N processors. In our second algorithm, we sort N numbers in O((log log N)/sup 2/) worst-case time using N/sup 1+/spl epsi// processors, for any fixed /spl epsi/ such that 0 < /spl epsi/ < 1. Our algorithms are based on a novel deterministic sampling scheme for merging two sorted arrays of length N each in O(log log N) time on an LARPBS with N processors. To our knowledge, the previous best sorting algorithm on this architecture has a running time of O((log N)/sup 2/) using N processors.

In the channel routing problem, terminals between cells are interconnected completely while reducing channel routing area. The crossing number, the number of crossings between two wires in the channel, is related to the channel routing area. In this paper, we present a parallel algorithm finding a maximum crossing number, density, in the channel by using a LARPBS model (Linear Array with a Reconfigurable Pipelined Bus System), which is based on the advanced fiber optic technology. The maximum crossing number algorithm on the LARPBS model runs in O(n) time using O(n) number of processors, where n is the number of nets in a channel.

In this paper, we present deterministic and probabilistic methods for simulating PRAM computations on linear arrays with reconfigurable pipelined bus systems (LARPBS). The following results are established in this paper. (1) Each step of a p-processor PRAM with meO(p) shared memory cells can be simulated by a p-processors LARPBS in O(log p) time, where the constant in the big-O notation is small. (2) Each step of a p-processor PRAM with meΩ(p) shared memory cells can be simulated by a p-processors LARPBS in O(log m) time. (3) Each step of a p-processor PRAM can be simulated by a p-processor LARPBS in O(log p) time with probability larger than 1−1/p^c for all c>0. (4) As an interesting byproduct, we show that a p-processor LARPBS can sort p items in O(log p) time, with a small constant hidden in the big-O notation. Our results indicate that an LARPBS can simulate a PRAM very efficiently.

We present efficient parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of parallel communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support parallel implementations of divide-and-conquer computations like Strassen's algorithm. The main contributions of the paper are as follows. We develop five matrix multiplication algorithms with varying degrees of parallelism on the LARPBS computing model; namely, MM/sub 1/, MM/sub 2/, MM/sub 3/, and compound algorithms C/sub 1/(/spl epsiv/)and C/sub 2/(/spl delta/). Algorithm C/sub 1/(/spl epsiv/) has adjustable time complexity in sublinear level. Algorithm C/sub 2/(/spl delta/) implies that it is feasible to achieve sublogarithmic time using /spl sigma/(N/sup 3/) processors for matrix multiplication on a realistic system. Algorithms MM/sub 3/, C/sub 1/(/spl epsiv/), and C/sub 2/(/spl delta/) all have o(/spl Nscr//sup 3/) cost and, hence, are very processor efficient. Algorithms MM/sub 1/, MM/sub 3/, and C/sub 1/(/spl epsiv/) are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM/sub 2/ and C/sub 2/(/spl delta/) are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM/sub 2/ and C/sub 2/(/spl delta/) to unbounded integers and reals are also discussed.

The optical bus based arrays have recently shown many applications. In this paper we use the pipelining ability of the LARPBS to solve the repetitions detection problem. We propose an algorithm that finds all kind of repetitions in a string including k-power repetitions, overlapping repetitions and non-contiguous repetitions. For a given distance, this operation is performed in O(1) communication cycle with a constant computation time processors on a O(n) processors LARPBS for a string of length n. For all the periods, it is O(n) bus cycle. No previous algorithms were known for this problem on the LARPBS.

Almost all of the existing two-dimensional block-based medial axis transform (2D_BB_MAT) parallel algorithm are devised for solving the 2D_BB_MAT problem only and are very difficult to extend to a solution of the 3D_BB_MAT problem in parallel. In this paper, we propose efficient O(1) time algorithms for solving the hD_BB_MAT problems, where h is 2 or 3, on the linear array with a reconfigurable pipelined bus system (LARPBS) model. The proposed 2D_BB_MAT algorithm can easily extend to a solution of the 3D_BB_MAT problem in parallel by reducing the hD_BB_MAT problems to the forward chessboard distance transform problems. To the best of our knowledge, the proposed algorithms are the most efficient O(1) time algorithms compared with all the previously published algorithms known.

Efficient and scalable quicksort on a linear array with a reconfigurable pipelined bus system

With the advent of optical fiber and other advanced technologies in solid state, pipelining signals at the wire (or transmission line) level has become possible. this has, in turn, made the slotted bus a potential candidate for interconnection networks (IN) for tightly coupled multiprocessor systems. However, a bus can provide only limited bandwidth. Though slotted bus can provide considerably more bandwidth in comparison to the traditional non-slotted bus, it is not enough for fine-grain parallel applications run on the shared-memory systems. One well known method to increase the effective bandwidth of a slotted bus in the LAN/MAN environment is to reuse the bandwidth by reusing slots. However, in a tightly coupled environment reusing slots is not a lucrative option because the significant buffering needs arising from slot reuse will introduce intolerable delay. In this paper we propose a methodology to reuse part of the bandwidth available from temporal and spectral bandwidth expansion with none or minimum buffering delay, resulting in significant performance improvement inboth the effective throughput and response time (communication latency). The proposed method entails the design and analysis of a re-configurable bus structure with both temporal and spectral bandwidth expansion and a polynomial time algorithm for optimal configurations for given traffic conditions. We have compared the performance of our reconfigured bus with that of the traditional slotted bus for uniform and localized traffic pattern and found that the reconfigured bus outperforms the traditional slotted bus substantially in many practical scenarios.

Constant time sorting on a processor array with a reconfigurable bus system

A constant time algorithm for finding maxima on reconfigurable bus systems using fewer processors

The reconfigurable mesh is a processor array that consists processors arranged in 1-dimensional or 2- dimensional grids with a reconfigurable bus system. The main contribution of this paper is to show initialization algorithms on the 1-dimensional reconfigurable mesh with n processors. We assume that processors are identical, and does not have unique IDs. Initialization is a task that assigns sequential IDs to processors in the reconfigurable mesh. We first show a simple deterministic initialization algorithm for the I-dimensional reconfigurable mesh that runs in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (n) time. This deterministic algorithm is optimal, because no deterministic solution can perform initialization in less than <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (n) time. Quite surprisingly, we show that expected sublinear-time initialization is possible if we use randomized techniques. Our initialization algorithm runs in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ((log n + log f) log log n) time with probability at least 1-1/4 for every real number f ges 1. It follows that the initialization algorithm runs in expected O(log n log log n) time. We also proved that any randomized initialization need to run in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (log n) time. Thus, our randomized initialization algorithm running in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (log n log log n) time is very close to a theoretical lower bound Omega(log n) time.

A mesh-connected computer enhanced by a reconfigurable bus system is referred to as a reconfigurable mesh (RM). Given an n×n grey-scale image and m×m template, in this paper, an O( log m) time parallel algorithm for template matching is presented on a RM with O(m2n2) processors. Suppose the image and template are binary, an O(1) time algorithm is presented on a RM with O(m3n2) processors. Both algorithms are superior to the best known algorithms on RMs.

Presents an efficient improvement of processor complexity while solving some connectivity problems in processor arrays with reconfigurable bus systems. We first derive two constant time algorithms in the proposed parallel processing system for computing the dominators and the dominator tree of an undirected graph either using a 9-D n/spl times/n/spl times/n processors or a 2-D n/sup 2//spl times/n/sup 2/ processors, where n is the number of vertices of the graph. Then based on the dominator tree algorithm, we also solve many other graph connectivity problems in constant time. They are the articulation points, bridges, biconnected components, and bridge-connected components problems in undirected graphs.

CAN bus communication system was established mainly using SimEvents module in the software of Matlab/Simulink. Performance indexes of CAN bus system, which embraces worst-case response time of messages and bus load, were separately gained by theoretical calculation, experiments in Matlab and CANoe. The calculation and experiment results were compared sufficiently, and it concludes that CAN bus system established in Matlab/Simulink can efficiently represent the message transfer sequences on the CAN bus, and achieve an exact result of the performance analysis of the CAN bus system. With CAN bus system established in Matlab/Simulink, test modules for ECU (Electric Control Unit) testing can conveniently be created, and it is an efficient testing tool for CAN bus system design.