Efficient Block-Based Medial Axis Transforms Based on L Metric

We present two fast algorithms for sorting on a linear array with a reconfigurable pipelined bus system (LARPBS), one of the recently proposed parallel architectures based on optical buses. In our first algorithm, we sort N numbers in O(log N log log N) worst-case time using N processors. In our second algorithm, we sort N numbers in O((log log N)/sup 2/) worst-case time using N/sup 1+/spl epsi// processors, for any fixed /spl epsi/ such that 0 < /spl epsi/ < 1. Our algorithms are based on a novel deterministic sampling scheme for merging two sorted arrays of length N each in O(log log N) time on an LARPBS with N processors. To our knowledge, the previous best sorting algorithm on this architecture has a running time of O((log N)/sup 2/) using N processors.

We present a fast algorithm for sorting on a linear array with a reconfigurable pipelined bus system (LARPBS), one of the recently proposed parallel architectures based on optical buses. Our algorithm sorts N numbers in O(log N log logN) worst-case time using N processors. To our knowledge, the previous best sorting algorithm on this architecture has a running time of O(log2N).KeywordsLinear ArrayRecursive CallSorting AlgorithmMerging AlgorithmDestination ProcessorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Efficient and scalable quicksort on a linear array with a reconfigurable pipelined bus system

In the channel routing problem, terminals between cells are interconnected completely while reducing channel routing area. The crossing number, the number of crossings between two wires in the channel, is related to the channel routing area. In this paper, we present a parallel algorithm finding a maximum crossing number, density, in the channel by using a LARPBS model (Linear Array with a Reconfigurable Pipelined Bus System), which is based on the advanced fiber optic technology. The maximum crossing number algorithm on the LARPBS model runs in O(n) time using O(n) number of processors, where n is the number of nets in a channel.

In this paper, we present deterministic and probabilistic methods for simulating PRAM computations on linear arrays with reconfigurable pipelined bus systems (LARPBS). The following results are established in this paper. (1) Each step of a p-processor PRAM with meO(p) shared memory cells can be simulated by a p-processors LARPBS in O(log p) time, where the constant in the big-O notation is small. (2) Each step of a p-processor PRAM with meΩ(p) shared memory cells can be simulated by a p-processors LARPBS in O(log m) time. (3) Each step of a p-processor PRAM can be simulated by a p-processor LARPBS in O(log p) time with probability larger than 1−1/p^c for all c>0. (4) As an interesting byproduct, we show that a p-processor LARPBS can sort p items in O(log p) time, with a small constant hidden in the big-O notation. Our results indicate that an LARPBS can simulate a PRAM very efficiently.

We present efficient parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of parallel communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support parallel implementations of divide-and-conquer computations like Strassen's algorithm. The main contributions of the paper are as follows. We develop five matrix multiplication algorithms with varying degrees of parallelism on the LARPBS computing model; namely, MM/sub 1/, MM/sub 2/, MM/sub 3/, and compound algorithms C/sub 1/(/spl epsiv/)and C/sub 2/(/spl delta/). Algorithm C/sub 1/(/spl epsiv/) has adjustable time complexity in sublinear level. Algorithm C/sub 2/(/spl delta/) implies that it is feasible to achieve sublogarithmic time using /spl sigma/(N/sup 3/) processors for matrix multiplication on a realistic system. Algorithms MM/sub 3/, C/sub 1/(/spl epsiv/), and C/sub 2/(/spl delta/) all have o(/spl Nscr//sup 3/) cost and, hence, are very processor efficient. Algorithms MM/sub 1/, MM/sub 3/, and C/sub 1/(/spl epsiv/) are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM/sub 2/ and C/sub 2/(/spl delta/) are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM/sub 2/ and C/sub 2/(/spl delta/) to unbounded integers and reals are also discussed.

In this paper, we present an efficient deterministic algorithm for sorting on the LARPBS (Linear Array with a Reconfigurable Pipelined Optical Bus System) model. Our sorting algorithm sorts n general keys in O(logn) time on a LARPBS of size nslogn. The previous best results can sort n items in O(lognloglogn) worst-case time using n processors or sort n items in O((log logn2)worst-case time using n1+ processors. Our algorithm is also scalable to certain extent. When the system size is reduced to nslogn/r for l≤r≤logn, the total computation time is O(rlogn).

The optical bus based arrays have recently shown many applications. In this paper we use the pipelining ability of the LARPBS to solve the repetitions detection problem. We propose an algorithm that finds all kind of repetitions in a string including k-power repetitions, overlapping repetitions and non-contiguous repetitions. For a given distance, this operation is performed in O(1) communication cycle with a constant computation time processors on a O(n) processors LARPBS for a string of length n. For all the periods, it is O(n) bus cycle. No previous algorithms were known for this problem on the LARPBS.

With the advent of optical fiber and other advanced technologies in solid state, pipelining signals at the wire (or transmission line) level has become possible. this has, in turn, made the slotted bus a potential candidate for interconnection networks (IN) for tightly coupled multiprocessor systems. However, a bus can provide only limited bandwidth. Though slotted bus can provide considerably more bandwidth in comparison to the traditional non-slotted bus, it is not enough for fine-grain parallel applications run on the shared-memory systems. One well known method to increase the effective bandwidth of a slotted bus in the LAN/MAN environment is to reuse the bandwidth by reusing slots. However, in a tightly coupled environment reusing slots is not a lucrative option because the significant buffering needs arising from slot reuse will introduce intolerable delay. In this paper we propose a methodology to reuse part of the bandwidth available from temporal and spectral bandwidth expansion with none or minimum buffering delay, resulting in significant performance improvement inboth the effective throughput and response time (communication latency). The proposed method entails the design and analysis of a re-configurable bus structure with both temporal and spectral bandwidth expansion and a polynomial time algorithm for optimal configurations for given traffic conditions. We have compared the performance of our reconfigured bus with that of the traditional slotted bus for uniform and localized traffic pattern and found that the reconfigured bus outperforms the traditional slotted bus substantially in many practical scenarios.

Recent work on the problem of mapping pipelined or parallel computations onto linear array, shared memory, and host-satellite systems is extended. It is shown how these problems can be solved even more efficiently when computation module execution times are bounded from below, intermodule communication times are bounded from above, and the processors satisfy certain homogeneity constraints. The improved algorithms have significantly lower time and space complexities than the more general algorithms: in one case, an O(nm/sup 3/) time algorithm for mapping m modules onto n processors is replaced with an O(nm log m) time algorithm, and the space requirements are reduced from O(nm/sup 2/) to O(m). Run-time complexity is reduced further with parallel mapping algorithms based on these improvements, which run on the architectures for which they create mappings.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient implementation of global computations on a linear array of processors is complicated due to the small communication bandwidth and the large communication diameter of the array. This paper presents efficient parallel techniques for partitioning, movement, and reduction of data on linear arrays. Also, efficient data structures are used to enable fast sequential access of query points within each processor. This combination of serial and parallel techniques is used to derive an optimal parallel algorithm for computing the convex hull of each connected region in an n×n image. The algorithm takes O(n 2/p) time on a linear array with p processors, where 1≤p≤n/log n. This result is processor-time optimal since an optimal sequential algorithm takes O(n 2) to solve the problem. Thus, a linear array with n/log n processors can solve the above problem in O(n log n) time. In comparison, a two dimensional mesh-connected array of processors can solve this problem in O(n) time using n 2 processors. The processor-time product for the mesh is O(n 3), which is not optimal.KeywordsConvex HullExtreme PointLinear ArrayLocal MemoryQuery PointThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

SummaryThe problem of designing efficient parallel algorithms to calculate the product of n numbers when the multipliers are large is a fundamental problem in many applications of computer science such as cryptography. In this work, we present a new parallel algorithm on exclusive read shared memory model. The performance of the introduced algorithm is measured based on three factors, namely, (1) the number of cores, (2) the size of the array, and (3) the size of the multiplier. The experimental study on a multi core system reveals that the introduced algorithm is faster than the best‐known optimal parallel algorithm. The improvement of the proposed algorithm in processing time compared to the best known parallel algorithm is 80% when the size of the array was 220 and the sizes of the multiplier were 1024, 2048, and 4096 bits. Moreover, our algorithm is a highly scalable parallel algorithm compared with the best‐known optimal parallel algorithm.

A mesh-connected computer enhanced by a reconfigurable bus system is referred to as a reconfigurable mesh (RM). Given an n×n grey-scale image and m×m template, in this paper, an O( log m) time parallel algorithm for template matching is presented on a RM with O(m2n2) processors. Suppose the image and template are binary, an O(1) time algorithm is presented on a RM with O(m3n2) processors. Both algorithms are superior to the best known algorithms on RMs.

The article presents a comparative analysis of the implementation of parallel algorithms on the central processors of automation systems in agriculture. Modern automation systems impose increased requirements on the reliability of the implementation of parallel algorithms in real time. It is proposed to use models for the development, analysis and comparison of parallel algorithms on GPUs. The proposed model of parallel computing on GPUs is designed to simplify the development of parallel algorithms for a heterogeneous CPU-GPU environment. Those, with this model, you can: develop parallel algorithms that use data parallelism, while applying the existing experience in creating parallel algorithms for the PRAM machine; evaluate the running time of the parallel algorithm and analyze which part of it is the most resource-intensive and requires optimization; compare parallel algorithms according to some parameters of the model, and, if required, select the best one according to these parameters in real time for automation in agriculture.

In this paper, we present a constant time algorithm for solving three dimensional block-based medial axis transform (3D BB-MAT, for short) on the array with reconfigurable optical buses (AROB). The main contribution of this work is to exploit the dominance counting method for solving the 3D BB-MAT that was never done previously in the literature. With the advantages of both optical transmission and electronic computation on the AROB model, the constant algorithm is proposed for the medial axis transform of a 3D N x N x N binary image on a 4D AROB using N^4 processors. To the best of our knowledge, this presented result of the dominance counting technique for medial axis transform of block-based is the best O(1) time algorithm known.