A cool packaging technology for power conversion application

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore's Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps' reliability, through-silicon vias' (TSVs) and redistribution layers' (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing.

Miniaturization is an essential requirement for development of space-borne electronics hardware. Recently, advancements in the device and packaging technology such as Analog Front End (AFE), FPGA and ASIC has enabled on-board designers to develop space worthy, high reliability miniaturized hardware meeting the functional and performance requirements. HMC, SIP, 3D packaging technology etc. can further miniaturize the hardware by embedding dice, devices, active and passive components. 3D packaging technology, which is ESA qualified, allows us to integrate packaged devices and printed circuit boards (PCB) with high reliability vertical interconnections. It is possible to migrate from existing PCB designs along with the same bill of material to 3D packaging technology. A development of miniaturized camera module consisting of 4K elements linear detector, detector drive electronics, analog video processing and digitizing electronics, timing and control logic along with serial data output has been carried out for space use using 3D packaging. Brief details of this camera hardware, development steps and realization challenges along with test results are given in this paper.

This paper reports 13.56 MHz and 27.1 MHz class-E amplifiers with a high voltage GaN-HEMT as the main switching device showing the possibility of GaN-HEMTs in high frequency switching power applications such as RF power-supply applications. The 380 V/1.9 A GaN power-HEMT was designed and fabricated for high-voltage power electronics applications. The demonstrated 13.56 MHz circuit achieved the output power of 13.4 W and the power efficiency of 91 % under a drain-peak voltage as high as 330 V. For a 27.1 MHz circuit, the output power was 13.8 W with the efficiency of 89.6 %. These results show that high voltage GaN-devices are suitable for high frequency switching applications under high DC input voltages of over 100 V

Wafer level packaging technology, as an advanced packaging technology with high maturity and wide application, has been widely used in portable products such as mobile communication. This paper mainly introduces two kinds of wafer level chip scale package forms, fan in and fan out, introduces the whole process of fan-out wafer level package and finally looks into the future development trend of wafer level chip scale package technology.

The continued need for higher density designs with advanced electronic packaging technologies such as Ball Grid Array (BGA) and Chip Scale Packaging (CSP) and other commercial component technologies are important to Raytheon. Due to the costs associated with the development of certain high performance products, there is a critical need within Raytheon to develop rework capability of assemblies using these technologies. Unlike the commercial arena which produces high volume - low cost products such as cell-phones, personal digital assistants (PDA), computers and digital cameras, to name a few, the products developed by Raytheon Electronic Systems are considered low volume - high cost. The economics of the commercial arena indicate that reworking an electronic assembly is more the exception than the rule, whereas rework is a critical requirement for Raytheon. This paper will cover BGA/CSP rework, the process of repairing/modifying Printed Wiring Boards (PWB) when using these packages and the benefits associated with having this capability. In addition, we will highlight some of the lessons learned through our in–house process development. These capabilities stem from the leveraging of packaging technology development of the JPL/NASA led consortium, which Raytheon has been a member for the past seven years.

Increasing demands for electronic devices with greater functionality, superior performance in more compact and smaller packages has driven the semiconductor industry to develop more advanced packaging technologies. To address the limitations of two-dimensional configuration (2D), which has been the traditional approach to IC integration, in the past few years, new emerging technologies have been developed. Vertical integration proved to be essential in achieving a greater integration flexibility of different technologies, disparate devices, reason for which a general trend of transition from 2D to three-dimensional (3D) integration is currently being observed in the industry [1-5]. Among all the different types of 3D packaging technologies, 3D chip integration using through silicon via (TSV) copper is considered one of the most advanced technologies, and certainly, one of the hottest topics in the industry today. There are different materials and methods that have been proposed and tested for TSV applications. Applicability of each material and method is limited by feature dimensions, final deposit characteristics and process reliability, practicability and last, but not least, cost considerations. Copper electrochemical deposition processes have several characteristics that make them attractive for various semiconductor applications, including TSV structure formation. This paper will address various copper electrodeposition processes applied to form 3D interconnects. Advantages and difficulties associated with each of these technologies and the approaches taken to overcome them will be presented. Reliable WLP structures of thick metal and high aspect ratios seem to be difficult to achieve when dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) are applied. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB), can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition for deep via filling, at significantly lower costs. TSV structures obtained with such techniques will be reviewed, along with the optimization work performed for achieving super conformal deep-via filling. Applying the optimum process parameters, void free TSV structures over a wide range of feature sizes and aspect ratios can be achieved. The effect of various factors that could considerably affect the performance, manufacturability and cost will be explained. Integrated costs estimations associated with TSV for a viafirst approach, including a breakdown of the process steps will be presented.

Integrated circuit packaging review with an emphasis on 3D packaging

Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFabricTM platform, the back end packaging technology Chip-on-Wafer-on-Substrate (CoWoS®) with the integration of High-Bandwidth Memory (HBM) has been successfully deployed in high performance compute and machine learning applications to achieve high compute throughput, while Integrated Fan-Out (InFO) packaging technology is widely used in mobile applications thanks to its small footprint. System on Integrated Chips (SoIC⃨), leveraging advanced front end Silicon process technology, offers an unprecedented bonding density for vertical stacking.

The third-generation power semiconductor silicon carbide half bridge power modules are widely applicable in various application scenarios, such as motor drive, photovoltaics and wind power inverters, tractions, electric vehicles, etc.. They possesses the advantages of high breakdown voltage, smaller dynamic parameters, and high operating temperature that is beneficial for power electronics system designs with higher switching frequency and improved power density. However, the external customized gate driver circuities designs could results in a relatively large parasitic inductance and resistance. In this work, a novel silicon carbide half-bridge power module (1200V/240A) with advanced packaging technology is proposed, which is a first-of-its-kind solution to tackle the coupled electrical-thermal challenges, including the monolithic low parasitic gate driver circuitry integration, ultra-low module stray inductance, improved power efficiency, thermal conductivity, and enhanced reliability, for advanced power electronics systems applications. The electrical and package design features will be thoroughly discussed. Electrical simulation results revealed that the gate drive loop resistance and inductance are respectively less than 7 mΩ and 60 nH, and the power module stray inductance is only around 10 nH (around 33% reduction compared to commercially available products). Moreover, the simulated junction-to-case thermal resistance is only 0.0785 K/W, and is favourable for simplifying the stringent cooling system design in power systems.

Triggers for high voltage (HV) switches have always been critical components for reliable, efficient pulsed power systems because they control the timing synchronization and amplitude variation of multiple pulse forming lines that combine to produce the total system output pulse. In pulsed power systems of the future, the role of trigger systems are even more critical as they trigger more components and produce shaped-pulses by independent timing of individual switches or switch groups. Conventional trigger systems require high voltage trigger cables or line-of-sight optics that complicate design, demand space, and require extensive maintenance. With electrical triggers, large diameter, high voltage transmission line cables must be fed through high field regions. With optical triggers, line-of-sight optics must focus high energy laser beams to the interior of the switches with clean, rigidly-mounted, shock- withstanding optics. This paper reports on efforts to develop fiber- optically triggered photoconductive semiconductor switches (PCSS) to trigger high voltage switches with improved precision and eliminate the need for large- diameter trigger cables or line-of-sight optics. These triggers simplify design because their optical-isolation allows them to "float" with the switches that they trigger and have truly independent EMP-free timing control over 200 micron diameter optical fibers. They improve the performance of prime power switches, diverters, and diagnostics because their low-jitter sub-nanosecond rise times are more precise and more easily adjusted than conventional trigger sources. For pulse charged switches, the PCSS triggers can generally derive their trigger energy from the stray fields of the high voltage switch. Test results will be presented that have demonstrated 100 ps r-m-s jitter from a 40 kV, 500 ps rise time, PCSS- triggered 300 kV trigatron gas gap. PCSS design requirements, switching properties, and trade-offs for building high voltage trigger systems will also be described based on many previous experiments with PCSS technology. Results from PCSS Blumlein and PCSS capacitive discharge pulsers will be discussed along with the designs to use these pulsers to trigger both DC and pulse charged high voltage switches.

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

The market demand of mobile electronic appliances is for smaller, lightweight physical characteristics with greater functionality. This demand contributes to advances in packaging technology that require semiconductor devices to be thinner to meet size and high thermal reliability constraints. Even though the active layer of most devices amounts for only 5-10 microns (with some devices needing about 20 microns to assure functionality of the device), the current thickness for new technologies such as ICs for smart card applications are around 150 microns. Based on current developments, the thickness of thinned wafers will start to approach 50 microns in the next couple of years. Therefore, it is not surprising that silicon thinning and stress relief have become important issues in the backend and assembly areas of semiconductor component manufacturers. Disco Corporation are developing new processes and pursuing industry initiatives to provide solutions to address these issues.

In order to keep up with scaling trends, significant efforts are being undertaken in the direction of vertical stacking of integrated circuits. With advancements in packaging technology, chips are being stacked atop each other using through-silicon-vias (TSVs). The fabrication process for TSVs on a silicon substrate for these 3D integrated circuits (ICs) introduces mechanical stresses that in turn affect the electrical parameters of the surrounding transistors depending on their orientation and distance from the TSV. This introduces significant variability in key performance metrics, especially when the devices operate at lower than nominal supply voltages. In this work, a complete methodology is developed to predict the impact on the delay of a buffer chain designed using Fin Field-Effect Transistors (FinFETs) around the TSV. First, an analytical model is developed to predict the normal stress components in the silicon wafer due to the TSV, which is subsequently converted in a layout-dependent model for variations in key device-level parameters. Subsequently, a modified logical effort-based model is proposed to predict the delay of a buffer chain designed around the TSV.

Pharmaceutical packaging is crucial for maintaining the safety, stability, and effectiveness of medications throughout their lifespan. Recent years have seen significant advancements in packaging technology, driven by innovations in smart packaging, sustainability, tamper-evident designs, and patient adherence. This review explores the latest developments in pharmaceutical packaging, including the use of digital technologies like RFID, QR codes, and IoT systems, as well as eco-friendly materials that support global sustainability initiatives. We also examine advanced evaluation methods, such as accelerated stability testing, compatibility studies, and regulatory compliance assessments, which help ensure packaging performance. These advancements aim to improve product tracking, user experience, and regulatory compliance, ultimately enhancing patient safety and satisfaction. By integrating technology, safety, and environmental considerations, the pharmaceutical industry can develop innovative packaging solutions that meet evolving needs and expectations.

Food packaging is designed to protect foods, to provide required information about the food, and to make food handling convenient for distribution to consumers. Packaging has a crucial role in the process of food quality, safety, and shelf-life extension. Possible interactions between food and packaging are important in what is concerning food quality and safety. This review tries to offer a picture of the most important types of active packaging emphasizing the controlled/target release antimicrobial and/or antioxidant packaging including system design, different methods of polymer matrix modification, and processing. The testing methods for the appreciation of the performance of active food packaging, as well as mechanisms and kinetics implied in active compounds release, are summarized. During the last years, many fast advancements in packaging technology appeared, including intelligent or smart packaging (IOSP), (i.e., time–temperature indicators (TTIs), gas indicators, radiofrequency identification (RFID), and others). Legislation is also discussed.