Physical Design for 3D Chiplets and System Integration

Advanced mobile computing devices nowadays demand for ever-increasing functionality, performance and bandwidth. The complexity of functional integration in mobile device has made it more challenging for wire bond and C4 bump flip chip packaging to meet the requirement of high I/O count and high density integration. Moreover, the extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) must be utilized to meet performance requirements from the advanced silicon technology nodes. In this paper, the maximum ELK stress for advanced mobile SoC integrated by different packaging technologies, aka integrated fan-out (InFO), chip last fan-out wafer level package (CL-FOWLP), and flip chip package, were evaluated by FEA first. Then the governing mechanisms behind the ELK stress were analyzed. The InFO outperforms CL-FOWLP and flip chip package in the maximum ELK stress due to its simplified architecture and fabrication process. With a low ELK stress, InFO technology can play an important role in enabling more advanced mobile ICs and high performance SoC packaging for the future 4C applications.

After the appearance of Apple’s A10 processor in 2015, advanced packaging technology based on the 12 inch wafer process has created a new market. Various new advanced packaging technologies have been developed, and many heterogeneous integration products have been appeared, becoming mainstream of the development of semiconductor technology. SK hynix has developed its own technology and is ahead of the market as an advanced packaging product that applies TSV(Through Silicon Via) such as HBM(High Bandwidth Memory). This paper introduced wafer molding, chip to wafer stacking, and processes that apply machine learning, which are unique mass production technologies of SK hynix.

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.

The study provides an examination of the use of mobile applications in English language learning among EFL learners. It explores the advantages, challenges, and limitations of mobile learning applications and their effectiveness in improving language skills. The research method used to conduct the study is a review of related literature for various studies conducted on the research topic. The study is also planned to examine the effectiveness of using mobile applications for English language learning by EFL learners. Also, the best practices for integrating mobile applications into EFL classrooms and provide insights into future possibilities for mobile language learning. It is hoped that the current attempt helps enrich the previous literature in the field of Mobile Assisted Language Learning with theoretical information related to the use of Mobile learning applications in learning the English language in an EFL context

The tremendous growth in smartphones and tablets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of integrated circuit (IC) devices, resulting in the need for more advanced and sophisticated packaging techniques. In particular, the integration of the application processor (AP) and dedicated memory has become increasingly complex. Smartphones and tablets have become virtual streaming devices requiring low power, high bandwidth memory (HBM). For quality, high-speed video and multi-tasking applications, the memory interface to the AP must have superior signal integrity to minimize crosstalk and insertion/return losses. In addition, the thermal management of the processor must allow the maximum clock speed and duty cycle for high-performance applications. Finally, to conserve battery life for the mobility device, the power distribution to the processor must be as efficient as possible. This creates a significant challenge for the semiconductor packaging industry to meet these demanding requirements for smartphone and tablet products. This paper introduces a leading-edge high-density fan-out (HD-FO) semiconductor packaging technology that addresses the need for higher levels of integration and improved electrical and thermal performance for mobile applications. This new innovative technique, called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging, leverages the fine feature size and thin-film circuit patterning capabilities of wafer-level packaging. In addition, thin-film dielectric photolithography and pattern plating provides a significant reduction in package z-height, which is critical for advanced mobile devices. By incorporating a redistribution layer (RDL)-first/chip-last process flow, there is also an opportunity for yield optimization and cycle-time reduction. This work compares the electrical and thermal modeling results between a conventional Package-on-Package (PoP) and HD-FO SWIFT devices. The results reveal a highly integrated PoP structure with exceptional electrical, mechanical, and thermal performance benefits – compared to conventional organic laminate-based technologies – to meet the growing need for high-performance mobile applications.

In mobile application, to integrate the required functions in the limited area is one of the key points of the success of the products. The industries have studied the way of integration method by adopting system on chip or system in package approach. With the conventional approach using laminate substrate, there had been the limit of integration due to its limited pattern capability and larger keep out zone for underfill. It’s known that fan-out package is one of the effective solutions to make the compact system. One of the most important factors is to achieve fine joint pitch to make the system within Package on Package format. In this study, the system integration by using advanced packaging technology like fan-out PLP will be provided. One of wearable devices had been selected to see the effect of integration. In conventional approach, the devices had been placed on main PCB, respectively. To make the area compact, some of PKG types were selected and compared. Finally, we had found the most effective package format for fine form factor.

An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of −53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.

High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) has emerged as a preferred choice for leading-edge graphics, networking and highperformance computing applications. HBM is also finding usage in artificial intelligence (AI), machine learning (ML) and other advanced applications that demand high bandwidth and high power efficiency. HBM systems are implemented in 2.5D technology in which the memory stack and System-on-Chip (SoC) are integrated using a silicon interposer in a single package. Unlike conventional Double Data Rate (DDR) systems, the memory channel in 2.5D HBM systems are not accessible outside the package, posing multiple challenges in post-silicon characterization, system validation and SoC bring up. This paper discusses the functional at-speed test challenges and solutions using IEEE1500 based test structures implemented in the PHY, complementing those in DRAM. The paper also discusses a novel method to allow channel pin access for receiver and transmitter characterization with minimal impact to normal operation. Silicon results are presented at different levels of system hierarchy that consists of Memory Controller (MC), Physical Layer (PHY) and DRAM. Together, these results demonstrate excellent test coverage of the complete HBM memory subsystem and efficient silicon debug support.

Power management relieves critical bottlenecks in saving electrical energy and efficient switching devices are particularly required for synchronous power conversion module. To optimize both switching and thermal efficiencies for convertor configuration it relies on the advanced package technology. An analysis has been undertaken in this work to identify the challenge on power electronic packages to ensure the system efficiencies continue to increase. This paper presents an innovative three-dimension (3D) packaging technology - CoolPAK, which enables high voltage, high frequency and high reliable voltage switching with reduced power loss in thermal dissipation.

Wafer level packaging technology, as an advanced packaging technology with high maturity and wide application, has been widely used in portable products such as mobile communication. This paper mainly introduces two kinds of wafer level chip scale package forms, fan in and fan out, introduces the whole process of fan-out wafer level package and finally looks into the future development trend of wafer level chip scale package technology.

A cost effective, easily scalable, and application independent FPGA cluster co-processing platform for machine learning (ML) applications is proposed. The work in this paper focuses on delivering an economical platform for the researchers and developers without the knowledge of FPGAs who seek budget friendly solutions to increase the performance of their ML applications without relying on the highly expensive solutions available in the today's FPGA market. The approach consists of two main parts, with a CPU based host machine learning application and the FPGA cluster sharing the heavy workload through an Ethernet protocol. An experiment was conducted using a perceptron layer implementation on the hardware and the test results show the execution time improvements due to the utilization of the proposed cluster approach. The solution proposed is easily scalable with any FPGA platform with an Ethernet support.

The continued need for higher density designs with advanced electronic packaging technologies such as Ball Grid Array (BGA) and Chip Scale Packaging (CSP) and other commercial component technologies are important to Raytheon. Due to the costs associated with the development of certain high performance products, there is a critical need within Raytheon to develop rework capability of assemblies using these technologies. Unlike the commercial arena which produces high volume - low cost products such as cell-phones, personal digital assistants (PDA), computers and digital cameras, to name a few, the products developed by Raytheon Electronic Systems are considered low volume - high cost. The economics of the commercial arena indicate that reworking an electronic assembly is more the exception than the rule, whereas rework is a critical requirement for Raytheon. This paper will cover BGA/CSP rework, the process of repairing/modifying Printed Wiring Boards (PWB) when using these packages and the benefits associated with having this capability. In addition, we will highlight some of the lessons learned through our in–house process development. These capabilities stem from the leveraging of packaging technology development of the JPL/NASA led consortium, which Raytheon has been a member for the past seven years.

Humanistic Buddhism has adopted more practical than theories and philosophy into our life. However, there are still weaknesses in teaching and learning Buddhism, especially in Buddhist schools in Asia and Asian American Communities. This study aims to develop mobile learning applications for humanistic Buddhism learning among young adults based on Phase 1(one) ADDIE Model, determine the behavioral acceptance and attitudes factors of mobile application to learn Humanistic Buddhism among youth. Methodology of study using ADDIE Model, finding of study indicates 28% of the respondents know the meaning of Humanistic Buddhism, 65% of the respondents were female respondents and 35% of the respondents were male, 78% of the respondents’ educational level were undergraduates. Attitude towards mobile learning, ‘I know the term of mobile learning’ 4.62 indicated that respondents had above moderate level in term of mobile learning whereas for the other item ‘I often stay focus in my mobile learning application’ 3.66 indicated that respondents had moderate level in staying focus in mobile learning applications. Mostly used application indicated that 59% of the respondents used Microsoft Team as a mobile learning application. Next, the purpose of use of mobile learning application ‘I use mobile learning applications to submit assignments’ 2.45 indicated that respondents below moderately agreed they use mobile learning applications to submit assignments. On the other hand, ‘I use mobile learning applications to participate in online classes’ 3.35 indicated that respondents moderately agreed they use mobile learning applications to participate in online classes. As for the mobile learning experiences, ‘I can access knowledge anywhere and anytime using the mobile learning applications’ 4.47 indicated that respondents below moderately agreed they can access knowledge anywhere and anytime using the mobile learning applications. The satisfaction toward mobile applications ‘rate your overall mobile learning experience’ 4.18 indicated that respondents had above moderate satisfaction on overall mobile learning experience. Apart from that, 30% of the respondents stated that connectivity to internet is poor which fits the biggest challenges of using mobile applications to learn. Hence, the goal of this study was to consider and comprehend the role of mobile learning in order to create new applications. It has given the results of an exploratory study of the knowledge of youth Buddhism toward concept of Humanistic Buddhism. This study showed that participants are open to adopting mobile learning and have a favorable view regarding it. As for future studies, it can be conducted with a sizable survey sample made up of teachers and administrators from all across the nation, as well as a variety of youth Buddhism.

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore's Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps' reliability, through-silicon vias' (TSVs) and redistribution layers' (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing.

As the demands of higher performance, higher bandwidth, lower power consumption as well as multiple functions increases in mobile applications, the mobile phone has evolved from a simple communication device to a complicated and highly integrated system with multiple functions and heterogeneous devices. Due to the fast growth in emerging markets for mobile applications, packaging technology has become more challenging than ever before, driving advanced Silicon (Si) nodes, finer bump pitch as well as finer line width and spacing substrate manufacturing capabilities to satisfy the increasing requirements in mobile devices. Flip chip chip scale package (fcCSP) is viewed as an attractive solution when higher input/output (I/O) counts in a package are needed. In order to enhance the performance, reduce the power consumption and increase transition rates, three-dimensional (3D) package-on-package solution with flip chip interconnect (fcPoP) has been widely utilized to successfully achieve these goals. With the ability to stack a logic processor and low power double data rate (LPDDR) memory device in a single package, the utilization of fcPoP is becoming a preferred solution in the mobile market segment for a better power and performance balance. However, as more and more functions are designed in a chip to target the high-end mobile market, the die is becoming larger and larger. With the larger die size, it is challenging for the regular fcPoP structure to support high bandwidth top memory I/O counts in a limited package size. In order to solve the constraints of larger die and/or package size limitations, top memory with wide I/O counts as well as customized mobile memory applications, high bandwidth fcPoP technology is proposed as an strong solution. This paper reports the development of a fine pitch high bandwidth fcPoP. The top interposer substrate with copper (Cu) post interconnections peripherally is connected to bottom package. The top interposer substrate can be designed in a different top and bottom pitch to connect top mobile memory and bottom packages, respectively. With this structure, die size limitations can be overcome by using finer interconnection pitch, providing the flexibility to allow any memory interface pitch application. In addition, through this developed result, not only the package warpage/coplanarity control and reliability characterization are illustrated, it also demonstrated this enabling technology of high bandwidth fcPoP as a highly integrated, miniaturized and low profile 3D packaging solution.