InFO (Wafer Level Integrated Fan-Out) Technology

Thin die fabrication is an essential part of wafer processes in 3D IC, interposer, and fan-in and fan-out wafer level packaging technologies. A review on the available process technologies including temporary bonding, de-bonding, wafer thinning, thin wafer handling, thin wafer backside processes, and die singulation are discussed and summarized in this chapter. The fabricated thin dies are integrated and assembled using wafer level system integration (WLSI) processes. A brief summary on two important WLSI technology platforms, namely Chip-on-Wafer-on-Substrate (CoWoS™) and Integrated Fan-Out (InFO) are presented as a conclusion for thin die fabrication and wafer level system integration chapter.

Advanced mobile computing devices nowadays demand for ever-increasing functionality, performance and bandwidth. The complexity of functional integration in mobile device has made it more challenging for wire bond and C4 bump flip chip packaging to meet the requirement of high I/O count and high density integration. Moreover, the extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) must be utilized to meet performance requirements from the advanced silicon technology nodes. In this paper, the maximum ELK stress for advanced mobile SoC integrated by different packaging technologies, aka integrated fan-out (InFO), chip last fan-out wafer level package (CL-FOWLP), and flip chip package, were evaluated by FEA first. Then the governing mechanisms behind the ELK stress were analyzed. The InFO outperforms CL-FOWLP and flip chip package in the maximum ELK stress due to its simplified architecture and fabrication process. With a low ELK stress, InFO technology can play an important role in enabling more advanced mobile ICs and high performance SoC packaging for the future 4C applications.

An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of −53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So it's necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP (system in package) technologies have been developed to satisfy these requests. The embedded packages are one or more chips are embedded at the inside of the substrate and one of the technologies to realize the packages with thin and small size and high performance but there is much room for improvement, such as reliability issues, yields, etc. Therefore, wafer level embedded SiP (WL-ESiP) which daughter chip is embedded on mother chip by mold compound without substrate has been developed. In this study, to confirm our wafer level embedded SiP structure and processes, feasibility test has been performed by fabrication of molded dies with 2 stacked dies at wafer level and verified by reliability tests of MSL2a, PCT (121?C/100%RH/2 atm), HTS (150?C) and TC (-65/150?C) for molded dies. To realize this embedded SiP, redistribution, solder and Cu bumping, flip-chip bonding, molding, Si and mold thinning and ball mounting technologies have been developed and applied at the wafer level. After feasibility test, to confirm the effect of the package size and material for the WL-ESiP, the reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) have been performed for molded dies with die sizes of 4 mm ? 4 mm and 6 mm ? 6 mm, 3 types of dielectric materials and 3 types of mold materials and the test vehicle with MC3 mold, D2 dielectric and 4 mm ? 4 mm size passed MSL2a, 168 hrs of PCT, 2000 cycles of TC and 1000 hrs of HTS. Also, the stress simulation of mold dies has been performed and the location with maximum stress has been confirmed. As a result of reliability tests and stress simulation for the molded die, WL ESiP test vehicle with daisy chain has been designed and fabricated to evaluate the package level and board level reliabilities. The size of mother and daughter chips is 4 mm ? 4 mm and 2.95 mm ? 2.31 mm respectively and daughter chip has 70 um thickness. For the fabricated WL-ESiP, package level reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) has been performed. And TC (-40/125?C) and drop (1500 G/0.5 ms) tests will be also performed at board level.

To apply WLP to various devices from small pin count to high pin count devices, various types of WLP have been developed and evaluated in terms of package size, structure and materials. Firstly for the application of small pin count, the reliability for Wafer Level Package of 6×6 ball array (36 balls) in 0.5mm pitch had been evaluated over TC (Temperature Cycling) and HTS (High Temperature Storage) at package level and passed. Then, the reliability for WLP of 9×9 ball array (65 balls, depopulated array) in 0.4mm pitch has been evaluated by employing TC, THT (Temperature Humidity Test), 4-point bending and Drop test at board level. All test items have been passed. To verify the application of high pin count devices, Wafer Level Packages of solder ball array 12×12 (144 balls) and 14×14 (196 balls) in 0.4mm pitch have been fabricated and tested over various reliability tests. Package level reliability tests for precondition level 3, multi-reflow, PCT, HTS and TC have been evaluated and passed. Board level reliability has been proven through various reliability tests. For one package for both small and high pin devices, Wafer Level System in Package(WLSiP) which has two chips inside one WLP has been developed. To optimize the structure and materials for WLSiP, various reliability tests had been performed in terms of die size and material type. According to the above results, WLSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliability tests.

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

Second level interconnect (SLI) or board level reliability (BLR) solder joint fatigue has been investigated extensively by OEM, ODM and OSAT. The influencing factors are well understood that package form factor (FF) and BGA pattern are primary factors. Modeling and testing correlate well in identifying failure location and predicting fatigue life. Previously bump level (FLI) is less touched due to large pitch and less fatigue reliability concerns. With the technology shift to more Chip Scale Package (CSP) FF and finer bump pitch, bump fatigue failure frequently occurs and meeting the reliability requirement become more challenging. However, even bump fatigue becomes more prominent, still not enough effort has been invested due to the modeling complexity when UF is present. As the first step towards developing bump fatigue life prediction, we carried out parametric finite element analysis (FEA) and investigated the factors from material, packaging design aspects that are often neglected in BLR. FEA study showed that with the presence of underfill, more factors than SLI/BLR influence the bump fatigue failure prediction. Key parameters that could affect failure location and life prediction are presented here.

A family of novel wafer-level-system-integration technologies (WLSI) was proposed. This paper reviews WLSI feasibility work first. Further results on the reliability, the compatibility of the integration with both more advanced node Logic and DRAM devices, and the higher-level system integration of the WLSI technologies are then presented. Foundry has established a comprehensive system integration technology portfolio in wafer form to fulfill the needs from mobile to cloud computing for the future growth of the Si-based nano-electronics industry.

The Chemical Mechanical Polishing (CMP) variation on a die is a function of the die’s location on the wafer. For example, the post CMP thickness and/or topography variations in the center die can be very different from those in the mid-radius and edge dies. Consequently, the number of CMP hotspots and the hotspot locations can vary from die-to-die on a given wafer. Most commercial CMP simulation tools in the Design for Manufacturing (DFM) field focus on predicting CMP topography and thicknesses for a single die on the patterned wafer, and do not have wafer level prediction capabilities. For CMP simulation to be more effective in process and layout optimization, CMP simulation tools should be able to accurately predict CMP performance at the feature-scale, within the die, and across the entire wafer. In this paper, we analyze CMP data from multiple dies on back end of line (BEOL) Cu interconnect levels and show the wafer level effects in a polishing process. We use the data to calibrate Cadence’s integrated wafer level and die level CMP models and use the calibrated models to predict the CMP pattern dependencies on multiple dies across a product chip wafer. Finally, we show a comparison of the simulation to measured data.

Compared to aluminum the electromigration resistance of copper is higher. This leads to longer test times. Higher acceleration factors are needed to reach reasonable test times. Because of the oven hardware there is a limitation in the stress temperature for standard iso-current tests on package level at 350/spl deg/C. Self-heated test methods, such as SWEAT and accelerated iso-current test on wafer level, use Joule-heating to to reach stress temperatures up to 600/spl deg/C and therefore to much lower test times. For aluminum a qualitative analysis with these tests has already been conducted successfully. It would be a major advantage, if quantitative analysis, e.g. extrapolation to operation conditions, would be feasible. During this investigation, we have used three different electromigration stress methods, iso-current test on package level, iso-current test on wafer level and SWEAT, with different stress conditions on the same structure and material. We show an extrapolation of all of the results of the different test methods to operation conditions and a way to calculate the necessary Black's parameters from the results of the highly accelerated self-heated tests.

This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

Wafer Level Chip Scale packages use packaging technology at the wafer level instead of traditional method of assembling individual devices in packages. WCSP boards are being extensively used in handheld devices due to its smaller form factor, low cost and high packaging efficiency. WCSP has a relatively short solder life compared to other packages and so the reliability of these packages are of great concern. A PCB is a multi-layered structure in which each layer has different material characteristics and has a significant effect on the board itself. Removal of layers or changing the composition of the layers affects the solder balls' life [1], thus impacting the solder joint reliability of the boards. One of the key parameters in board level reliability is thermal cycling and during thermal cycling, stress is accumulated in the solders due to warpage of the board caused by coefficient of thermal expansion (CTE) and modulus mismatch between the layers [2-3]. This paper will try to address the possible effect of individual layers during thermal cycling by considering layer removal and by considering boards with different thickness created.

Current industry trends in the microelectronics packaging is going towards increasing in I/O density and small size packaging. Common use of solder material in packaging are the lead free solders. The popular lead free alloys include the SnAgCu (SAC) family such as SAC 305 and SC405. SAC solder alloys are favor due to high stains rate transient load and reliable operation at high temperature. Hence, it is suitable for application such as military application, avionics, and automotive [1], [2]. SAC alloy is frequently used in Wafer Level Chip Scale Package designs but achieving board level reliability especially when footprint go beyond a certain size causes challenge for SAC solder ball [3]. To overcome this issues, new type of solder alloy, SACQ and QSAC, has been established in current market to improve board level reliability performance. In this paper, studies of the 2nd level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work. In this paper, studies of the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work.

The emergence and evolution of any package technology is driven by market trends as experienced by the end application. With the maturation of the mobile market, the trends for Smartphone and other mobile devices are more than ever for lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices are, higher performance designs, lower cost, smaller form factor, and higher level of integration. The advancement of silicon scaling to 14/16 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. Earlier in 2012, eWLB Package-on-Package (eWLB-PoP) technology delivered a 30% height reduction in PoP, reducing the overall stacked package height from the industry standard 1.4mm to 1.0mm. Through further innovations in eWLB technology, a 40% height reduction in the bottom PoP architecture has been achieved. An ultra thin z-height of 0.3mm was realized in 2013, thereby providing the advantage of having an overall PoP package height as low as 0.8mm with proven board level reliability. While traditional PoP solutions are widely used in the high-end mobility market, demand is accelerating for ultra thin, cost effective packages that have the flexibility to serve a range of applications from mid-range to low-end mobile phones as well as tablets that require significantly higher processor speeds. While printed circuit board (PCB) substrate technology limits the interconnection density of a PoP package to 200-300 input/output (I/O), eWLB-based PoP solutions can deliver beyond 500 I/O in an overall thinner package with a dense vertical interconnection and wider interface to stack memory packages on the top. This paper reports developments that extend 3D PoP and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Various test vehicles have been designed and fabricated to demonstrate these low profile solutions for mobile, portable and wearable electronics. The test vehicles have ranged from medium to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including embedded Bar (eBar), laser ablation, interconnect processes and mechanical characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on 3D eWLB-PoP / eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.