Structure and process development of wafer level embedded SiP (System in Package) for mobile applications

To apply WLP to various devices from small pin count to high pin count devices, various types of WLP have been developed and evaluated in terms of package size, structure and materials. Firstly for the application of small pin count, the reliability for Wafer Level Package of 6×6 ball array (36 balls) in 0.5mm pitch had been evaluated over TC (Temperature Cycling) and HTS (High Temperature Storage) at package level and passed. Then, the reliability for WLP of 9×9 ball array (65 balls, depopulated array) in 0.4mm pitch has been evaluated by employing TC, THT (Temperature Humidity Test), 4-point bending and Drop test at board level. All test items have been passed. To verify the application of high pin count devices, Wafer Level Packages of solder ball array 12×12 (144 balls) and 14×14 (196 balls) in 0.4mm pitch have been fabricated and tested over various reliability tests. Package level reliability tests for precondition level 3, multi-reflow, PCT, HTS and TC have been evaluated and passed. Board level reliability has been proven through various reliability tests. For one package for both small and high pin devices, Wafer Level System in Package(WLSiP) which has two chips inside one WLP has been developed. To optimize the structure and materials for WLSiP, various reliability tests had been performed in terms of die size and material type. According to the above results, WLSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliability tests.

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

The emergence and evolution of any package technology is driven by market trends as experienced by the end application. With the maturation of the mobile market, the trends for Smartphone and other mobile devices are more than ever for lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices are, higher performance designs, lower cost, smaller form factor, and higher level of integration. The advancement of silicon scaling to 14/16 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. Earlier in 2012, eWLB Package-on-Package (eWLB-PoP) technology delivered a 30% height reduction in PoP, reducing the overall stacked package height from the industry standard 1.4mm to 1.0mm. Through further innovations in eWLB technology, a 40% height reduction in the bottom PoP architecture has been achieved. An ultra thin z-height of 0.3mm was realized in 2013, thereby providing the advantage of having an overall PoP package height as low as 0.8mm with proven board level reliability. While traditional PoP solutions are widely used in the high-end mobility market, demand is accelerating for ultra thin, cost effective packages that have the flexibility to serve a range of applications from mid-range to low-end mobile phones as well as tablets that require significantly higher processor speeds. While printed circuit board (PCB) substrate technology limits the interconnection density of a PoP package to 200-300 input/output (I/O), eWLB-based PoP solutions can deliver beyond 500 I/O in an overall thinner package with a dense vertical interconnection and wider interface to stack memory packages on the top. This paper reports developments that extend 3D PoP and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Various test vehicles have been designed and fabricated to demonstrate these low profile solutions for mobile, portable and wearable electronics. The test vehicles have ranged from medium to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including embedded Bar (eBar), laser ablation, interconnect processes and mechanical characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on 3D eWLB-PoP / eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

The automotive market for the IC (integrated circuit) packaging industry has grown significantly over the last 8 to 10 years due to its increasing need for automation, higher performance, and the more stringent reliability requirements in the vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent at a reasonable cost. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced and more reliable packages for next generation automotive market requirements. Automotive IC’s have traditionally been assembled in mature wirebond type packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards very high performance flip chip, fan out wafer level and very recently system in package (SiP) solutions for automotive ADAS, infotainment, GPS, camera, radar, driverless car and many more applications. SiP packages or modules are getting more momentum for complex functionality for high computing automotive such as L3 or L4 automotive. In this study a comprehensive view of the changing packaging landscape from standard flip chip interconnect to highly complex SiP or module packages and the corresponding reliability grade level requirements (G2, G1) will be discussed. Special design, process and BOM (bill of materials) are the most important parameters to consider for high reliability, complex SiPs for automotive applications. In this study, detailed design parameters, step-by-step package development, along with the optimal BOM are evaluated. Both package and board level data were analyzed to qualify automotive SiP for G2 and G1 conditions. Relative packaging cost vs performance for traditional packages to advanced SiPs are evaluated in the study.

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.

In this study, the board level reliability (BLR) performance of different copper (Cu) post wafer level package (WLP) structures without epoxy or molding encapsulation have been evaluated and compared to standard WLP. The Cu post WLP test vehicle has been performed on different stack up structures of 4.7 x 7.1 mm2 package size at 0.4 mm ball pitch. The Cu post bumps of test vehicles were manufactured through main-stream production technologies including standard ball drop and electro-plated lead free solder after Cu post completed. The Cu post WLP will enhance the risk of board level solder joint fatigue due to thick Cu post without encapsulation will increase bump site stress. The optimized design parameters of package stack up with low temperature cured polyimide are implemented to accommodate the increased stress. In this work, we also evaluated a novel Cu post WLP stack up structure for fast package cycle time and fine pitch application. The improved BLR performance of large die size Cu post WLP is demonstrated in this investigation. The failure modes analysis and Weibull failure statistics are presented for the BLR results and recommendations as to the preferred Cu post WLP structure are also included.

The system-in-package (SiP) is widely used in communication device that integrated multi components and packages into one system. However, the board level reliability performance becomes more important, especially cyclic bending test. In the work, both experimental and numerical model are performed to investigate the four point cyclic bending test with different load displacement. The bending test experiment was analyzed by Weibull method to calculate the solder fatigue life of SiP module. A three-dimension finite element method (FEM) and the Anand's visco-plasticity Model are used to simulate solder's creep behavior under cyclic bending test. It was constructed and experimentally benchmarked to qualitatively figure out solder joint failure location in whole package and crack position in solder interconnection. Besides, the constructive index, plastic work density (PWD) accumulated per cycle, is used to evaluate the risk of solder fatigue cracking failure and be correlated well from experimental characteristic cycles. This work provides design guideline for SiP module board level reliability under bending test. The factors that underfill dispensing effect and material type suggestion are also considered in this work.

A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8/spl times/8 array of bumps on a 5/spl times/5 mm/sup 2/ die. Micro Moire Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported.

For getting more economy and smaller electronic products, technology of system in package (SiP) could complement the technology of system on a chip (SoC) perfectly. About SiP technology, we chose integral substrate technology to realize embedded passives, and used fine process such as high density interconnection (HDI) technology with a special dielectric material to achieve specific circuit functions. The special material is a high dielectric constant (Hi-DK; DK>40 @ 1GHz) material, which is suitable for Multi-Layer Printed Wiring Board (PWB) lamination process, and it was used to fulfill embedded capacitors. In the past years, we had utilized the technology to design Bluetooth/sup TM/ module, or other RF circuits. Furthermore, this technology is more economy than any other SiP processes, like Low Temperature Co-fired Ceramic (LTCC) substrate or silicon substrate, because it bases on the conventional PCB process. In this paper, we introduce not only the embedded capacitors but also some functional embedded passives in RF front-end circuits design on the Hi-DK organic substrate. Moreover, the RF front-end circuits include some functional passive elements: band pass filter, balun, and antenna, etc. Thus, in high frequency circuits, this kind organic substrate can reduce the module size, and in high-speed digital circuits, it also provides inexpensive decoupling capacitors. In the future, we will use this cost-effective technology to design analog and digital circuits on the same board, and the technology of SiP and SoC can be co-designed.

Wafer level encapsulation is an important packaging process for several components in mobile and high-performance computing applications. In mobile applications, electronic components like application processors, radio-frequency System in Package (RF-SiP) and antenna modules are being manufactured using wafer level fan-out processes. In HPC, wafer level encapsulation is used for chip-on-wafer (CoW) processing and 2.5D / 3D packaging that enables wafer level packaging of processors and high band width memory devices. Although encapsulant materials are currently used in mass production, many pain points remain unresolved. These are predominantly related to lowering the wafer level warpage to enable better handling of wafers during processing, addressing the environmental and EU REACH regulatory compliance, providing better total cost of ownership to the end user by improving throughput and various other factors. In our development, we aim to address these pains and we will present our progress in this research paper. As the structural material in the package, molding compound can cause severe warpage issue during process, becoming the limiting factor to pursue thinner packaging design and causing serious wafer handling issues in the equipment during wafer processing. However, we considered a new material design route to develop ultra-low warpage LCM materials that can dramatically reduce the warpage thereby benefitting various WLP packaging design, such as Fan-in or Fan-out type. We have successfully demonstrated more than 70% improvement in warpage compared to traditional LCM compound. This new type of LCM material is REACH compliant and shows good warpage stability after high temperature annealing process. The polymer relaxation study shows the unique relaxation behavior leading to the warpage stability that is critical in many Fan-out processes. Dynamic Mechanical Analysis is the useful tool to study the relaxation behavior that can differentiate the impact of various chemistry on epoxy molding materials. Another key advantage of our LCM is the excellent gapfilling capability that can lead to the protection of high density structures in semiconductor packages with finer die-to-die or die-to-substrate spacing, meanwhile enabling low-warpage and simpler processing steps. Moreover, the new LCM design can help further shorten the molding time, allowing for increased throughput resulting in lower cost of ownership for the end users.

This paper discusses the Design for Reliability modelling of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermo-mechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.

Ball shear testing is typically conducted on Wafer level chip scale package (WLCSP) fabrication to estimate the strength of the solder ball attachment. Generally, the solder ball shear strength is dependent on the solder ball size, pad size, solder/pad interface treatment, reflow temperature and time. Solder ball strength is also a function of ram speed and height at which the ball is sheared with respect to the wafer. Recent investigations suggest that ball shear test is being used as an indicator for board level reliability of assemblies. In current market lead time for launching a new product is very short. Unfortunately, it takes several weeks to qualify a new product by board level qualification process. If there is a methodology through which one can predict the board level performance by extrapolating the wafer level test, it will save great amount of resources in testing and millions of dollars worth of testing time. In this study, we conducted a wafer level ball shear tests and the study was validated computationally. A DOE was created for varying wafer level structural parameters like solder ball size and type, dielectric thickness and type of UBM. Ball shear tests are often easy to perform in the fabrication routine and are very important to check the process reliability.

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100µm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200µm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250µm BGA at 400µm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moire warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.