Functional embedded RF circuits on multi-layer printed wiring board (PWB) process

Adoption of fine pitch and high lead count area array components in high-reliability applications such as military and space electronics demands high-density interconnect (HDI) features in multilayer printed wiring boards (PWBs). Usage of cap-plated fine vias that are plugged with dielectric material is one of the approaches to meet the circuit density requirements. In this article, a novel method called “integral plugged blind via” without secondary processing steps, such as curing and planarization, is described to realize HDI multilayer PWBs. In this method, through vias are epoxy plugged during the lamination of inner layer circuits in vacuum-assisted hydraulic press cycle. Plugged blind vias are formed as an integral part of the fabrication process. It is observed that there is no excess ooze out of resin material from the blind vias in the laminated substrate and blind vias are found to have a negligible dimple and no voids. This is attributed to the gasket effect due to the elastomeric property of specialty release films, which conform (follow) to the contour of plated through vias during the vacuum lamination cycle. Plugged blind vias are subjected to critical thermomechanical stress to evaluate interconnection integrity. It is found that there is negligible change in the resistance of vias and resin plugged vias are free from defects such as barrel crack or knee crack of plated through hole (PTH) or delamination in the cured plugged material. Robustness of these resin-filled blind vias is attributed to anchored plated barrel with the additional support provided by plugged material, which restricts the thermomechanical deformation of plated copper.

In multi-layer printed wiring boards (PWBs), electrical connections between different layers are accomplished with plated through holes (PTHs). The reliability of the PTH barrel and the PTH-inner plane (IP) connection depends not only on the design but also on the conditions of manufacturing and assembly processes of the board. The concerns associated with manufacturing arise from drilling which heats up and smears the surrounding epoxy onto the copper inner plane surfaces and also from subsequent chemical hole-clean operations which desmear the drilled holes. Good adhesion of the PTH copper to the desmeared PTH wall and to the copper inner planes is important for the reliability of the PTHs during assembly and field service. PWB coupons consisting of resin-glass bundle areas as well as resin filled clearance areas surrounding the PTH have been considered for a series of experiments and tests. On these coupons, accelerated stress tests and failure analysis of the PTHs at the end of these tests have been conducted. An elasto-plastic finite element analysis of the PTH strains for a temperature excursion of 102°C has been carried out for signal PTHs without and with IP connections. A peel test, using a micro-mechanical tester, has also been carried out to assess the adhesion of PTH copper to different regions along the drilled hole. All of the testing techniques have been supplemented by suitable analytical techniques for studying the distribution of smear on the copper inner planes. A birefringence technique to estimate the temperature of the hole wall during drilling has been described. All of the fails observed during stress testing are in the form of cracks in the PTH barrel, the plane of the crack being perpendicular to the barrel axis. The cracks are localized near the glass bundle-resin rich interface. It has also been observed in the failure analysis that the PTH/IP connections are not susceptible to failure during the accelerated stress testing conditions considered. These observations are also supported by the results of stress analysis. The results of stress analysis show that the interior clearance holes show higher strains than those closer to board surfaces, suggesting that the PTH barrel failure is likely to occur at the clearance hole and that the likelihood of failure at the interior clearance holes is higher than those closer to the PWB surfaces. The results of the peel test reveal that in the glass bundle-resin regions, the adhesion along the PTH wall is determined by the mechanical interlocking between the plated copper and the glass bundles and is relatively insensitive to desmear operations. However, adhesion in the resin-rich areas is a strong function of the desmear operation, which enhances the adhesion of the PTH to the resin. Finally, it is shown that the birefringence technique may be used effectively to estimate the drilling temperature and, hence, the degree of smearing and PTH quality. It is concluded that while smear may play an important role in the failure of PTHs in PWBs, for thick packaging boards with high aspect ratio PTHs, the predominant failure mechanism is less likely to be smear related. Such a failure mechanism would be preceded by failure in the PTH barrels as a result of the large strain concentrations imposed at specific locations within the cross-section.

A plated-through hole (PTH) in multi-layer printed wiring boards (PWB) is defined as hole in which electrical connection is made between internal or external conductive patterns, or both, by plating of metal on the wall of the hole. The recent trend to increase the packaging density at all levels has resulted in a significant increase in PWB wiring layers and in turn for PTH density in order to communicate between the layers of circuitry. The increase in overall PCB thickness, coupled to the decrease in PTH diameter makes the PTH integrity during the assembly process and subsequent field stresses one of the primary reliability concerns in PWB production and usage. Thermo-mechanical stresses mainly due to mismatch in out-of-plane (z-direction) coefficient of thermal expansion (CTE) between the PTH metal and the laminated material can result in the failure of the PTHs. Failure of a PTH constitutes an electrical discontinuity which may be caused by fracture of the plating material at the barrel, fracture at the land-barrel junction, or delamination of the plating from the PWB. This paper will discuss the reliability performance of the PTHs when subjected to T/C (Temperature Cycle) stresses. During the initial reliability stressing through 1000 T/C 'B' (-55 to 125/spl deg/C) and T/C 'C' (-65 to 150/spl deg/C) electrical opens were observed. Physical analysis showed that the opens were due to barrel cracking of the PTHs. Extensive mechanical modeling and experimental validation were used to suggest changes in the materials, process and design to eliminate barrel cracking in high aspect ratio PTHs. Results of these analyses will be discussed in detail.

Rigid/flex multilayer printed wiring boards are more sensitive to thermal environmental changes than conventional printed wiring boards. This is manifested because of a composition of dissimilar materials used within the construction of this type of product. During fabrication and assembly, stresses can develop within the plated-through holes from differences in thermal properties of the rigid and flexible materials, primarily thermal coefficient of expansion. Thermal shock and thermal stress tests and rework simulation as defined in MIL-P-50884 have been performed in this study as indicators of processing quality to detect faults and to verify improvements in board reliability. 3 refs., 17 figs., 3 tabs.

As a concept, “System in Package” or “SiP” relates to the objective of merging many or all of the electronic requirements of a functional system or a subsystem into one package. It is a concept that can at once be understood by people familiar with electronics and packaging yet is very difficult to define in absolute terms. Amkor uses the following attributes to define SiPs: Includes chip-level interconnect technology. In other words flip chip, wirebond, TAB, or other interconnect directly to an IC chip. This distinguishes small SMT board assemblies from being considered SiPs. More often than not, the SiP is small in physical size. Quite often includes passive components. The passives can be either surface mounted discrete components or can be embedded into or manufactured on the substrate material. Typically includes more than one IC chip. May include other components necessary to bring the SiP to a more complete functional system or subsystem level – such as housings, lids, RF shields, connectors, antennas, batteries, etc Quite often the term System-in-Package is used to describe multi-chip IC packages such as stacked die CSPs or MCM-PBGAs. The real power of SiP technology lies in its ability to integrate not only multiple ICs but also other components such as passives, connectors, antennas and so on into the package in order to create fully functional subsystems. System in Package has a parallel in the often-discussed System on Chip (SoC) methodology. While SoC has many good attributes, and has been the focus of several IC manufacturers for several years, by its very nature it is limited by what can be achieved within one wafer process. It is quite easy to understand that SoC may be limited in the type of IC functions that one would like to design into a system – or at best performance will likely be compromised due to a common wafer process. SiP is not limited by the constraint of a common wafer process, so that IC chips, each optimally suited for its function by both design and wafer fab process, can be easily combined together in one package (for example a CMOS digital IC with a GaAs HBT RF IC). There are several reasons why the market demand seems to be growing strongly for SiP solutions. These include: Size: The size of sub-system can be reduced by integrating multiple ICs and other components in an SiP Time to market: It is often faster combine ICs in an SiP than it is to implement SoC at the IC level. It is also faster to make changes to the system at the SiP level than to change the entire mask set of an SOC solution. SIP implementation is faster than tune & debug at system board level, especially in RF applications, (e.g. cell phones) SiP solutions reduce the complexity of the motherboard by moving the routing complexity to the package substrate. This often results in reduced layer count in the motherboard and simplifies product design. Performance advantages: – e.g. ASIC or CPU to memory data speed enhancements by combining the logic and memory chips close to one another in the SiP. Another example is power reduction by minimizing line lengths (capacitive loads) between IC's in a SiP. For RF & Wireless SiPs – the package is literally a part of the circuit and the package design and materials selection can have a great impact on whether the RF circuit functions as intended. Fully integrated “plug and play” SiP solutions enable system designers to implement additional functions, such as Bluetooth or camera modules, into a system with minimal design effort. Lower System Cost: An optimized SiP solution usually results in an overall system cost reduction compared to discrete IC packages. SiP enables the system designer to mix and match IC technology in order to optimize the performance of each functional block. Note that SoC and SiP are not mutually exclusive, but SiP offers more flexibility in IC partitioning to optimize performance and cost.

The lamination process determines the quality of low temperature co-fired ceramics (LTCC) based spatial structures. This paper compares two methods of the microchannel fabrication process in zero-shrinkage LTCC substrates. The first one is based on a two-step lamination process and uses various sacrificial volume materials (SVM). The second one is based on the cold chemical lamination (CCL) process. On the one hand, the SVM gives the possibility of decreasing the deformation of the three-dimensional (3D) structures during the lamination process. The channel volume is filled with a special fugitive material. It protects the spatial structure from deformation during lamination, and evaporates completely during the co-firing process. The bonding quality and strength depend strongly on the fugitive phase type. On the other hand, the CCL is a solvent-based method. It is another alternative for bonding of green ceramic tapes. A special liquid agent is screen printed on the green tape, which melts the tape surface. Then the tapes are stacked and compressed at room temperature by a printing roll. The influence of each method on the microchannel geometry is analyzed in this paper. The resulting structures' bonding quality and mechanical properties are examined by a scanning electron microscope (SEM).

The motivation to further miniaturize and reduce the cost of portable electric devices has recently focused on the task of integration of the passive functions. In this paper, implications for integrating inductors and capacitors with standard multi-layer printed wiring board (PWB) lamination processes on organic substrates is discussed. To improve the circuit performance and obtain greater benefits of the integral passives, a multi-dielectric substrate with layer-specific dielectric constant and thickness is used to fulfill the designing of various integral passives. With these different material characteristics, we extract electrical parameters such as dielectric constant and loss tangent versus frequency of the special materials and then design various integral passives in a 6-layer multi-dielectric PWB substrate. Finally the potential advantages of using the PWB process on organic substrate with integral passives for a Bluetooth (BT) module are demonstrated.

Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer's substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.

Preliminary assessment of the stability of thin- and polymer thick-film resistors embedded into printed wiring boards

Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So it's necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP (system in package) technologies have been developed to satisfy these requests. The embedded packages are one or more chips are embedded at the inside of the substrate and one of the technologies to realize the packages with thin and small size and high performance but there is much room for improvement, such as reliability issues, yields, etc. Therefore, wafer level embedded SiP (WL-ESiP) which daughter chip is embedded on mother chip by mold compound without substrate has been developed. In this study, to confirm our wafer level embedded SiP structure and processes, feasibility test has been performed by fabrication of molded dies with 2 stacked dies at wafer level and verified by reliability tests of MSL2a, PCT (121?C/100%RH/2 atm), HTS (150?C) and TC (-65/150?C) for molded dies. To realize this embedded SiP, redistribution, solder and Cu bumping, flip-chip bonding, molding, Si and mold thinning and ball mounting technologies have been developed and applied at the wafer level. After feasibility test, to confirm the effect of the package size and material for the WL-ESiP, the reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) have been performed for molded dies with die sizes of 4 mm ? 4 mm and 6 mm ? 6 mm, 3 types of dielectric materials and 3 types of mold materials and the test vehicle with MC3 mold, D2 dielectric and 4 mm ? 4 mm size passed MSL2a, 168 hrs of PCT, 2000 cycles of TC and 1000 hrs of HTS. Also, the stress simulation of mold dies has been performed and the location with maximum stress has been confirmed. As a result of reliability tests and stress simulation for the molded die, WL ESiP test vehicle with daisy chain has been designed and fabricated to evaluate the package level and board level reliabilities. The size of mother and daughter chips is 4 mm ? 4 mm and 2.95 mm ? 2.31 mm respectively and daughter chip has 70 um thickness. For the fabricated WL-ESiP, package level reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) has been performed. And TC (-40/125?C) and drop (1500 G/0.5 ms) tests will be also performed at board level.

Recent progresses in miniaturization of sensors and actuators have yielded to the first attempt to create an mm3 -sized autonomous robot with sensing capabilities called I-SWARM. The robot is conceived to interact with other I-SWARM robots in order to create a robotic swarm. It is provided with a locomotion unit, an infrared communication system, a contact sensor, solar cells for powering, and a system on chip (SoC) that acts as the brain of the robot. All these components are mounted over a flexible printed circuit board, being I-SWARM a real system in package (SiP). The SoC communicates with other I-SWARMs, sense its environment, processes data and takes decisions, as for example moving, with less than 1.5 mW. Different electronic circuits (power electronics, buffers, ADCs, DACs, control units, analog transducers, and even an oscillator) have been embedded in the SoC due to the limited area, less than 3 × 3 mm2. The SoC is reprogrammable optically in order to change the behavior of the microrobot.

Smart ICT (Information and Communication Technology) such as "Big Data", "Cloud computing" and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and PWB (printed wiring board) packaging as high-density interposer are among key technologies to satisfy the requirements from the both smart semiconductor devices for AI (artificial intelligence), and smart functional devices for "Edge-computing". Meanwhile MEMS/Sensors are required as multi-functionalities of stand-alone smart devices for wearable devices including smart phone, an important part of smart-systems. Thus, the demand of high density FO-SiP (fan-out system in packaging) is growing. In order to accomplish high-density packaging as homogeneous and heterogeneous integration, miniaturization of wiring in organic package is needful to MCM (multi chip module) system fabrication on the PWB. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line/space because of laser wave length limitation. The second is that wet desmear process to remove smear for each generation's build-up films is also will be issue by swelling and silica-residue problem. And finally, such kind of technologies cannot intentionally control of surface roughness for build-up film. In this study, a fine via and line and space patterns processing below 10 μm with low surface-roughness in a low-CTE (coefficient of thermal expansion) Build-up film was achieved by using a plasma dry process. That technology applications are dry desmear and dry etching for fan-out wiring fabrication.

One of the key applications for foldable flex is to enable the use of 3-D (3Dimensional) MCMs (Multi-Chip Modules). This embodiment of a 3-D electronic package (E-package) represents the ultimate in packing density and it should be used whenever it benefits the application. The use of any MCM, however, brings up the issue of SoC (System-on-a-Chip) versus SiP (System-ina-Package). By its very nature, an MCM implies that the entire system is not on a single chip. Is eliminating all instances of an MCM what the SoC advocates mean when they so cavalierly bandy about the SoC acronym or can many SoCs exist on an MCM? Is the latter what the E-packaging community calls an SiP or is an SiP a more numerous collection of sub-SoCs (i.e., chips that are not SoCs) and/or SoCs on many single chip modules (SCMs) or one or more MCMs? These questions are very confusing and these questions are what will be explored in this chapter.

特集・多層プリント配線板，有機薄膜多層板を用いたＭＣＭ ＲＩＳＣワークステーション用ＭＣＭ‐Ｌの設計

Over the past several decades the quest to design electronics that boast ever increasing capabilities while continuously decreasing their size and weight has led to the development of a series of new packaging solutions. As the need for more functionality in less real estate increased, Multiple Chip Modules (MCM) were no longer satisfactory in many applications. Today, these applications call for a highly integrated packaging approach which often incorporates multiple functionalities into one package. In situations where time to the market for SOC (System on a Chip) is too slow or too costly the approach of System-in-a-package (SIP) can be the ideal solution. One element in modern packaging is the use of new 3D structures and high-k dielectric materials. The second element is advanced packaging methods. New technologies such as chip-on-chip assemblies have been developed. The third element has been the progression in design tools that allow engineers to seamlessly design an overall, highly integrated system. The forth element, testing, is often an expensive part of product development. With SIP technology that cost can be significantly lowered, making new product development economically more feasible. In this paper we present a systematic approach to designing highly integrated and miniaturized SIP packages. This approach enables rapid design, prototyping and time to production while achieving a new level of integration, miniaturization and reliability. Finally, a case study is presented to demonstrate a typical maturity cycle of a SIP, in this case for a wireless application.