An Optically Programmable SoC for an Autonomous Mobile mm$^{3}$-Sized Microrobot

Flexible electronics and sensors are a key enabling element for the realization of wearables and geometry adaptive devices needed to follow current trends such as the Internet of things or Industry 4.0. Within this paper, we present a new and flexible packaging platform by the fabrication of an ultra-thin and highly flexible printed circuit board (PCB).The thermoplastic polymer Parylene, which combines a variety of unique properties such as optical transparency, biostability and biocompatibility according to ISO 10993, thermal stability as well as low permeability for gases and water, was used as the base for the new PCB.Particularly, its mechanical properties, especially the absence of intrinsic stresses, as well as its low Young’s modulus and good bendability are advantageous when using Parylene films as a free-standing substrate for flexible applications. The chemical inertness of Parylene against all common acids, bases and solvents ensures its compatibility with established standard microsystem technologies.For the realization of ultra-thin flexible PCBs, Parylene was used as a substrate as well as for the encapsulation and protection layer, respectively. Furthermore, Parylene was the dielectric between the metallic conductive layers. These redistribution layers (RDL) were deposited and patterned by standard microsystem technologies, such as sputtering, lithography and wet chemical etching. Hence, structure sizes of down to 10 µm were successfully realized. Different metals, such as gold, copper, and aluminum were tested for the RDL. Alternatively, printing technologies such as screen printing and aerosol jet printing were successfully demonstrated for the if conductive silver layerse. The electrical connection between the various RDL was of special interest throughout the study and was realized by etching vertical vias through the Parylene using oxygen plasma. Due to the low total thickness of the flexible Parylene PCB of 20 µm or even less, the obtained vias through the Parylene feature an advantageous low aspect ratio. For the contact formation through the vias, different methods were investigated, e. g. sputtering, printing and electrochemical deposition.Finally, the fabricated flexible Parylene PCB were characterized with respect to their bendability and electrical properties. Doing so, the resistivity and capacitance were measured as well as the frequency response between 20 kHz and 500 MHz. Particularly, for frequencies below 1 MHz the realized flexible Parylene PCBs show a good electrical performance.A third function of Parylene with respect to the realization of an ultra-thin and flexible PCB is its usage as a barrier or capping layer. Doing so, new approaches such as embedding electronic or sensor components in the flexible PCB can be enabled. Other integration technologies such as wire bonding, printing or gluing were investigated with respect to their usability for the new flexible PCB as well. Besides, also the direct fabrication of sensors on the Parylene flexible PCB was successfully demonstrated by the realization of a flexible potentiometric pH sensor.The presented new type of ultra-thin PCB is a versatile platform for the realization of flexible electronics, sensors and devices. Due to its biocompatible properties, the flexible Parylene PCB can be used for medical applications but also for the integration of MEMS, chemical sensors and optical components, respectively. Doing so, it enables the realization of smart systems for wearable applications and their integration into light weight constructions. Within this paper, the concept of this new approach, the respected fabrication and integration technologies as well as possible applications are presented in detail. Figure 1

As a concept, “System in Package” or “SiP” relates to the objective of merging many or all of the electronic requirements of a functional system or a subsystem into one package. It is a concept that can at once be understood by people familiar with electronics and packaging yet is very difficult to define in absolute terms. Amkor uses the following attributes to define SiPs: Includes chip-level interconnect technology. In other words flip chip, wirebond, TAB, or other interconnect directly to an IC chip. This distinguishes small SMT board assemblies from being considered SiPs. More often than not, the SiP is small in physical size. Quite often includes passive components. The passives can be either surface mounted discrete components or can be embedded into or manufactured on the substrate material. Typically includes more than one IC chip. May include other components necessary to bring the SiP to a more complete functional system or subsystem level – such as housings, lids, RF shields, connectors, antennas, batteries, etc Quite often the term System-in-Package is used to describe multi-chip IC packages such as stacked die CSPs or MCM-PBGAs. The real power of SiP technology lies in its ability to integrate not only multiple ICs but also other components such as passives, connectors, antennas and so on into the package in order to create fully functional subsystems. System in Package has a parallel in the often-discussed System on Chip (SoC) methodology. While SoC has many good attributes, and has been the focus of several IC manufacturers for several years, by its very nature it is limited by what can be achieved within one wafer process. It is quite easy to understand that SoC may be limited in the type of IC functions that one would like to design into a system – or at best performance will likely be compromised due to a common wafer process. SiP is not limited by the constraint of a common wafer process, so that IC chips, each optimally suited for its function by both design and wafer fab process, can be easily combined together in one package (for example a CMOS digital IC with a GaAs HBT RF IC). There are several reasons why the market demand seems to be growing strongly for SiP solutions. These include: Size: The size of sub-system can be reduced by integrating multiple ICs and other components in an SiP Time to market: It is often faster combine ICs in an SiP than it is to implement SoC at the IC level. It is also faster to make changes to the system at the SiP level than to change the entire mask set of an SOC solution. SIP implementation is faster than tune & debug at system board level, especially in RF applications, (e.g. cell phones) SiP solutions reduce the complexity of the motherboard by moving the routing complexity to the package substrate. This often results in reduced layer count in the motherboard and simplifies product design. Performance advantages: – e.g. ASIC or CPU to memory data speed enhancements by combining the logic and memory chips close to one another in the SiP. Another example is power reduction by minimizing line lengths (capacitive loads) between IC's in a SiP. For RF & Wireless SiPs – the package is literally a part of the circuit and the package design and materials selection can have a great impact on whether the RF circuit functions as intended. Fully integrated “plug and play” SiP solutions enable system designers to implement additional functions, such as Bluetooth or camera modules, into a system with minimal design effort. Lower System Cost: An optimized SiP solution usually results in an overall system cost reduction compared to discrete IC packages. SiP enables the system designer to mix and match IC technology in order to optimize the performance of each functional block. Note that SoC and SiP are not mutually exclusive, but SiP offers more flexibility in IC partitioning to optimize performance and cost.

This paper presents a System On Chip (SoC) designed specifically to control a mm³- sized microrobot called I-SWARM. The robot is intended to be part of a colony of 1000 I-SWARM robots for studying swarm behavior in real time and in a real swarm. The SoC offers a well-suited hardware platform to run multi-agent systems software. It is composed of an 8051 microcontroller with 2 kB of data memory and 8 kB of program memory. The processor is provided with specific hardware modules for controlling the locomotion unit, the communications and the vibrating contact sensor of the robot. These modules perform basic tasks as movements or communications so the 8051 can focus on processing data and taking decisions. With these capabilities, the robot is able to avoiding collisions with other members of the swarm, performing cooperative tasks, sharing information and executing specialized tasks. The SoC has been fabricated with a 0.13 &mgr;m ultra low power CMOS process of STMicroelectronics and consumes less than 1 mW.

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

For getting more economy and smaller electronic products, technology of system in package (SiP) could complement the technology of system on a chip (SoC) perfectly. About SiP technology, we chose integral substrate technology to realize embedded passives, and used fine process such as high density interconnection (HDI) technology with a special dielectric material to achieve specific circuit functions. The special material is a high dielectric constant (Hi-DK; DK>40 @ 1GHz) material, which is suitable for Multi-Layer Printed Wiring Board (PWB) lamination process, and it was used to fulfill embedded capacitors. In the past years, we had utilized the technology to design Bluetooth/sup TM/ module, or other RF circuits. Furthermore, this technology is more economy than any other SiP processes, like Low Temperature Co-fired Ceramic (LTCC) substrate or silicon substrate, because it bases on the conventional PCB process. In this paper, we introduce not only the embedded capacitors but also some functional embedded passives in RF front-end circuits design on the Hi-DK organic substrate. Moreover, the RF front-end circuits include some functional passive elements: band pass filter, balun, and antenna, etc. Thus, in high frequency circuits, this kind organic substrate can reduce the module size, and in high-speed digital circuits, it also provides inexpensive decoupling capacitors. In the future, we will use this cost-effective technology to design analog and digital circuits on the same board, and the technology of SiP and SoC can be co-designed.

The ubiquity of complex devices built on systems on chip (SoC) with multiple processor cores poses new challenges for developers of embedded systems. New development tools specifically designed for complex systems on chip can help solve them, but these tools are usually limited by the functionality of debugging support tools. High-quality debugging support with advanced features is necessary to take full advantage of complex SoC devices while reducing development time. The article discusses various mechanisms and ways to implement support for debugging systems on chip designed for complex real-time systems used, for example, in the Internet of Things (IoT) paradigm. This review includes an assessment of the available solutions and their suitability for use with the next generation of complex systems on chip with multiple processor cores. It is shown that many existing solutions do not allow developers to easily take advantage of complex functions integrated into the next-generation SoC. The basic debugging support functions for multicore SoCs are summarized and discussed. Recommendations are given for SoC develo­pers and for the future direction of research in this area in order to provide a more suitable basis for new development tools. Such tools are extremely necessary for all embedded hard real-time systems and are of high importance for minimizing the complexity of their development. Modern systems and devices implementing the Internet of Things paradigm are increasingly required to have sufficiently high real-time performance while maintaining low power consumption. These requirements lead to the cre­ation of multicore SoC solutions with support for a wide range of peripheral devices and communication protocols. The systems are limited by the requirements for working in harsh conditions, such as, for example, in the engine compart­ment of a car or on a radar tower. The development of embedded hard real-time systems, in which a task that fails to be completed on time can lead to physical damage of the device, is a complex process. Effective tools, such as interactive debuggers and profilers, are an integral part of solving these problems and are vital for developing reliable embedded systems. Modern technologies now allow the integration of the entire system on a single silicon chip, known as a system on a chip (SoC), which leads to the relocation of existing external interfaces, widely used for development purposes, to the chip. Traditionally, communication within an embedded system is carried out using an external processor system bus, which is implemented in the form of tracks on a printed circuit board. The printed circuit board must support the appropriate interfaces of development tools that require a physical connection, such as, for example, logic analyzers and oscilloscopes. Previously, placing exter­nal interfaces on a chip left fewer options for external analysis tools and, in fact, makes developers "blind" to the internal state of the SoC. Without a reliable and consistent representation of the state of the embedded system, the detection of defects or errors in the system may become difficult or even impossible. The main solution to the problem of the lack of external interfaces is to provide access to internal nodes from outside the system through existing interfaces. There are many different approaches to achieving the required visibility, and they are outlined in this review.

FlashSoldering is a new innovative, non-contact, localized reflow soldering process initially developed for terminating fine insulated copper magnet wires to electronic contacts without first removing the wire insulation. Subsequent research has extended FlashSoldering applications to joining fine magnet wires to high-speed data connectors, joining flexible ribbon cables to rigid printed circuit boards (PCB), and reflow soldering miniature surface mount (SMT) components and connectors to flexible or rigid PCB's. Four elements comprise the FlashSoldering System. The first element is the substrate, which can be a flexible or rigid PCB. The second element is the SMT component or connector with “gull wing” style leads or a flexible ribbon cable. The third element is a precise amount of solder. The solder is plated onto both the substrate or component leads or is mechanically attached to the component or connector leads in the form of a solder bearing “nugget” which may contain flux. Solder can also be applied in the form of a precise amount of dispensed solder paste. The fourth and final element is a diode laser heat source. Non-contact diode laser heat reflows the solder plating or solder bearing “nugget” on the SMT component to the substrate to complete the solder joint. Applications for FlashSoldering include: single and multiple toroidal transformer packaging; LAN filters; low power DC-DC converters; woven or braided high speed data cables; and miniature temperature sensitive SMT components, connectors, and flexible ribbon cable attachment to rigid or flexible PCB's.

Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer's substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.

One of the key applications for foldable flex is to enable the use of 3-D (3Dimensional) MCMs (Multi-Chip Modules). This embodiment of a 3-D electronic package (E-package) represents the ultimate in packing density and it should be used whenever it benefits the application. The use of any MCM, however, brings up the issue of SoC (System-on-a-Chip) versus SiP (System-ina-Package). By its very nature, an MCM implies that the entire system is not on a single chip. Is eliminating all instances of an MCM what the SoC advocates mean when they so cavalierly bandy about the SoC acronym or can many SoCs exist on an MCM? Is the latter what the E-packaging community calls an SiP or is an SiP a more numerous collection of sub-SoCs (i.e., chips that are not SoCs) and/or SoCs on many single chip modules (SCMs) or one or more MCMs? These questions are very confusing and these questions are what will be explored in this chapter.

Internet of things (IoT) will influence all areas from consumer to health care to building and home automation and to observation. IoT enables direct communication between objects via internet. The main functional blocks of IoT devices are sensing, data transmitting, processing and analysis and subsequent actuation. As a result such a system will consist of sensors, actuators, wireless connection, data processing, power management, energy harvesting, memory and software. A total market volume of almost 400 Bio US$ is predicted for 2024 whereof about 12Bio US$ are expected for IoT sensors (Yole2014)). The main challenges are to reduce footprint (e.g. wearables, swarm), reduce costs of system, improve reliability and provide better performance. For example the costs of today's smart sensor systems are in the 100–1000US$ range and for 2024 an ASP in the 1US$ $ level is expected (Yole2014). To enable this, a high level of integration is needed for the next generations of IoT sensors. This will on one hand reduce costs and form factor but also enable multi sensors devices. More than Moore integration of functions offers the potential to meet both performance and cost targets for mass-market adoption. In addition to SoC (System on Chip) and SiP (System in Package) heterogeneous 3D integrations will be key enablers. 3D integration with the main technology bricks like TSV (Through Silicon Via), RDL (Redistribution Layer), D2W (Die to Wafer) and W2W (Wafer to Wafer) stacking and embedding allows to combine different technologies - different CMOS notes, MEMS, photonics, etc. At the same time expensive single die packaging can be avoided. The presentation will focus on reviewing 3D integration technologies and their potential for IoT from the perspective of a sensor solution provider.

This paper introduces a multi-channels data synchronous acquisition and processing IP (intellectual property) core for digital protective relay. It integrates data acquisition and processing in one FPGA, resolving problem of asynchrony between data acquisition and data processing as well as setting of the number of sampling channels and sampling points per period. In contrast to the traditional acquisition system, it has characteristic of high speed, flexibility and low cost. This IP core was verified in FPGA (field programmable gate array) based hardware platform. The result of experiment indicates that this IP core is correct and can be used into SOC (system on chip) application as a single module.

Advances in System on Chip (SoC) and System in Package (SiP) that draw upon experiences gained from nano, bio and photon based technologies have created a new domain that permits fabrication of multiplicity of independent technologies as part of 3D hyper-integrated System on System (SoS) platform. Recent advances in nonlinear optics supported by fabrication and experimental work on the extreme nonlinear optical behavior of nano-scale waveguides with high linear and nonlinear index materials has opened new horizons for chip-size photonics devices. These devices can be incorporated within SoC and SoS configurations as part of the optical layer, providing an ideal platform for fabrication of compact all-in-one optoelectronic devices within the 3D multi-layered SoS technology.

Over the past several decades the quest to design electronics that boast ever increasing capabilities while continuously decreasing their size and weight has led to the development of a series of new packaging solutions. As the need for more functionality in less real estate increased, Multiple Chip Modules (MCM) were no longer satisfactory in many applications. Today, these applications call for a highly integrated packaging approach which often incorporates multiple functionalities into one package. In situations where time to the market for SOC (System on a Chip) is too slow or too costly the approach of System-in-a-package (SIP) can be the ideal solution. One element in modern packaging is the use of new 3D structures and high-k dielectric materials. The second element is advanced packaging methods. New technologies such as chip-on-chip assemblies have been developed. The third element has been the progression in design tools that allow engineers to seamlessly design an overall, highly integrated system. The forth element, testing, is often an expensive part of product development. With SIP technology that cost can be significantly lowered, making new product development economically more feasible. In this paper we present a systematic approach to designing highly integrated and miniaturized SIP packages. This approach enables rapid design, prototyping and time to production while achieving a new level of integration, miniaturization and reliability. Finally, a case study is presented to demonstrate a typical maturity cycle of a SIP, in this case for a wireless application.

Functional materials for powering and implementing next-generation miniature sensors

This paper presents a fully implantable brain machine interface based on a new CMOS system-on-a-chip (SOC) including a low-power multi-channel current-reuse analog front-end (AFE), a multi-band wireless transceiver and a power management unit retrieving power from a 13.56 MHz carrier through a new 5-coil inductive link. In addition to this SOC, the proposed interface includes a low-power microcontroller, a wideband antenna and a double-sided power recovery coil. All components are bonded on a thin flexible printed circuit board. The AFE uses a new current-reuse circuit topology based on a current-mirror opamp which is scalable to very large number of recording channels, thanks to its small implementation area and its low-power consumption. It includes a low-noise amplifier (LNA) and a programmable gain amplifier (PGA) presenting tree selectable gains of 35 dB, 43.1 dB and 49.5 dB. The SOC is fabricated in a CMOS 180-nm process and has a size of 1.3 mm × 1.8 mm. The AFE has a low-power consumption of 9 µW (4.5 µw for LNA and 4.5 µw for PGA) per channel, for an input referred noise of 3.2 µV. A 5-coil wireless power link is utilized with an efficiency of 28% and a maximum power delivered to the load of 81 mW through a 1 cm2 flexible coil. The ultra wideband edge combining BPSK transmitter reaches a maximum data rate of 800 Mbps at 6.7 pJ/bit, and the 2.4-GHz OOK receiver reaches a maximum data rate of 100 Mbps. The whole system consumes 12.3 mW and weights 0.163 g. Finally, we present biological results obtained in-vivo from the cortex of an anesthetized mouse.