Encapsulated double-bump WL-CSP: design and reliability

WL-CSP reliability with various solder alloys and die thicknesses

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

Wafer level CSP (WLCSP) has been paid great attention due to its miniature size. It is a real chip size package from the package perspective. It is also a known good encapsulated die (KGED) from the die perspective. This means that the boundary between package and bare die becomes indistinct. It sometimes referred to as a 'packageless' package. It is no longer meaningless to enquire whether CSP or bare die should be used since WLCSP is emerging. WLCSP is shaped by wafer level packaging (WLP) and wafer level testing (WLT). At this time, eight WLCSPs are proposed using different kinds of WLP. Three WLT are also proposed, including the authors' own technology. We developed the Super CSP/sup TM/ using a unique WLP with five major processes: re-routing, metal-post forming, compression moulding, solder ball placing and dicing. This package allows a system designer to layout a motherboard at the smallest area possible. It also allows an assembly engineer to mount on a motherboard and replace from the motherboard similar to conventional CSPs, and allows a test engineer to test and burn-in much more easily than with known good die (KGD). We confirmed excellent electrical performance, package reliability, mountability, and second level packaging reliability.

To solve the mystery of early thermal cycling failures on a relatively small size (1.6 mm × 2.4 mm) wafer level chip scale package (WLCSP) with bump on re-passivation (BOR) structure, details of bump geometry parameters are looked into. While the under bump metal layer stack is first confirmed within specifications, UBM offset from center point is found greater than typical on the failed units. To fully understand the impact of this bump parameter shift that is defined by lithographic process, additional geometric configurations of the bump structure and materials, as well as bump parameter deviations are studied on the stress in solder, UBM and on chip SiN passivations. The study takes into consideration the thickness/size of UBM, aluminum metal pad, SiN passivation layer and PI re-passivation layer. UBM materials, such as nickel vs copper, are also included in the study. Board-level thermal cycling test (TMCL) is conducted on a WLCSP with 8×8 bump array at 0.4mm pitch. Simulation reveals that size ratio and bump offset indeed change the stress level in the critical passivation layer, and the results well explain the early failures recorded in a device qualification reliability test and follow up experimental verifications. Conclusion of this work should be applied when defining design rules for robust reliability performance and manufacturability of this traditional WLCSP bumping technology.

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

Chip Scale Packaging (CSP) has captured the attention of every semiconductor and printed circuit board manufacturer, but relatively few CSPs are in full production. Unlike the PCB surface mount assembly process, the wafer level portion of the CSP industry (and in particular, the back end process) lacks standards. As a result, suppliers and customers have disparate requirements. This poses a unique challenge for CSP manufacturers and equipment suppliers to develop an integrated back-end-of-the-line that provides high volume and flexibility with little changeover time and low reconfiguration costs. The back-end process we describe includes polymer coating, solder ball placement, laser marking, singulation, testing, and tape & reel. All of these are performed at the wafer level. The polymer coating process is used to define the grid array openings on the packaged devices with 0.3 mm solder balls on 0.5 mm pitch. Laser marking is incorporated with the requirement of producing alphanumeric and two-dimensional cell codes on both silicon and glass wafers. The unique requirement for singulation is to minimize the displacement of bumped die during the dicing and cleaning process. This is to minimize potential misalignment of the die during test. In order to test a diced wafer at the wafer level, we have worked with a vendor to supply a handler that can accept dicing film frames and compensate for die misalignments. Lastly, traditional tape & reel machines are not suitable for bulk packaging of small, wafer level devices. We have purchased a modified die taping/sorting machine and have designed a custom tape pocket. All versions of the Intarsia wafer level CSP are fully surface-mount compatible and are designed to allow a wide assembly process window with existing placement equipment and technologies. Board level assembly issues unique to CSPs will be also discussed.

Wafer level encapsulation is an important packaging process for several components in mobile and high-performance computing applications. In mobile applications, electronic components like application processors, radio-frequency System in Package (RF-SiP) and antenna modules are being manufactured using wafer level fan-out processes. In HPC, wafer level encapsulation is used for chip-on-wafer (CoW) processing and 2.5D / 3D packaging that enables wafer level packaging of processors and high band width memory devices. Although encapsulant materials are currently used in mass production, many pain points remain unresolved. These are predominantly related to lowering the wafer level warpage to enable better handling of wafers during processing, addressing the environmental and EU REACH regulatory compliance, providing better total cost of ownership to the end user by improving throughput and various other factors. In our development, we aim to address these pains and we will present our progress in this research paper. As the structural material in the package, molding compound can cause severe warpage issue during process, becoming the limiting factor to pursue thinner packaging design and causing serious wafer handling issues in the equipment during wafer processing. However, we considered a new material design route to develop ultra-low warpage LCM materials that can dramatically reduce the warpage thereby benefitting various WLP packaging design, such as Fan-in or Fan-out type. We have successfully demonstrated more than 70% improvement in warpage compared to traditional LCM compound. This new type of LCM material is REACH compliant and shows good warpage stability after high temperature annealing process. The polymer relaxation study shows the unique relaxation behavior leading to the warpage stability that is critical in many Fan-out processes. Dynamic Mechanical Analysis is the useful tool to study the relaxation behavior that can differentiate the impact of various chemistry on epoxy molding materials. Another key advantage of our LCM is the excellent gapfilling capability that can lead to the protection of high density structures in semiconductor packages with finer die-to-die or die-to-substrate spacing, meanwhile enabling low-warpage and simpler processing steps. Moreover, the new LCM design can help further shorten the molding time, allowing for increased throughput resulting in lower cost of ownership for the end users.

Wafer Level Packaging (WLP) has started to shine and played a prominent role in recent years in both semiconductor and Integrated Circuit (IC) field, especially in now thriving Micro-Electro-Mechanical System (MEMS) applications on account of its distinctive operating mechanism and adaptive design variety. In this study, several crucial WLP technologies are disclosed in detail, including Wafer to Wafer (W2W) bonding, wafer level wire bonding, wafer level compound molding and lapping. Simplified and conceptual process flow of MEMS WLP and development approaches are introduced and explained. Furthermore, relevant experimental results and technology characteristics, including glass frit printing and bonding results & shear strength in W2W bonding technology, wire shift & vertical loop height & ball shear & wire pull in wafer level wire bonding technology, Thickness to Thickness Variation (TTV) & wire sweep & warpage in wafer level compound molding technology, have also been extensively demonstrated. After MEMS WLP packaging process, device performance is then determined by the difference of voltage readout with the implementation of Wafer Level Dynamic Test (WLDT) before and after Highly Accelerated Stress Test (HAST), and the wafer device yield is also presented.

A low process temperature, hermetic and reliable Wafer Level Packaging (WLP) technology is required for Image Sensor Module (ISM) Packaging. Eutectic bonding is regarded as one of the most common used methods for WLP. Au-Sn metallization system has been applied as a wafer level bonding technology in many applications, but it still has process temperature around 300°C which is not applicable for temperature senstive materials contained device wafer like ISM. In this paper, a fluxless Au-In solder system with Au, In multilayer metallizations has been developed and fabrication process is also presented, the metallization is achieved using e-beam evaporation, test vehicle was then prepared for bonding quality evaluation. Bonding process is performed at 180°C with static force for a relatively long dwelling time of 30minutes in N2 ambience, finally a void free joint is formed. Microstructure observation reveals a combination of different Au-In intermetallic compounds AuIn2 and AuIn at the interface. Shear strength around 2OMPa could be obtained for as-bonded samples, and a remelting temperature over 300°C is confirmed using Thermomechanical Analysis (TMA) test. Real time Helium leak rate test are performed to check hermeticity of the package, samples are also subjected to Pressure Cooker Test (PCT) for evaluation of bonding performance after reliability test.

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

For development and design of high performance ICs, more and more functions are required to be contained in a chip scale package (CSP) for applications that require low profiles and small footprints. With thinner package profile requirements, thinner substrates are necessary. More reliability issues arise with thinner substrates to provide mechanical support. The different kinds of substrate design layout induce different stress distributions which affect the IC directly during various assembly processes. These propagating effects may finally cause die crack damage. Therefore, proper substrate layout design does not only achieve thermal and electrical functional requirements, but also prevents critical mechanical problems. The purpose of this paper is to investigate mechanical effects on the IC of different substrate design patterns. Furthermore, to improve the influence of the optimal substrate layout, a dummy copper layer is used within the substrate. For comparison and confirmation of these phenomena, both numerical analysis (FEA) and experiment measurements were employed. CSPs were used as the test vehicle. Effects of dummy patterns were observed during the assembly process. There is no chip damage observed with modified substrate design. For further investigation of other possible factors, substrate thickness was varied in the FEA model. It was proved that the design effect is insignificant with thicker substrates. A similar result was observed with parameters of chip thickness, and Moire interferometry was engaged to verify FEA models.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

A new low cost 3 Dimensional Wafer Level Chip Scale Package (3D-WLCSP) technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly is presented. This paper provides an overview of the new 3D-WLCSP technology including Flip Chip on wafer bonding assembly technologies required to produce the 3D Face to Face Flip Chip on wafer package. Development efforts are focused on high density flip chip placement forming the 3D-WLCSP and the associated innovations that this type of packaging and assembly includes. In this work, the flip chip pitch and bump size is varied as well as key assembly materials (including fluxes and underfills) used to attach the flip chip to the WLCSP. Processing innovations developed include flip chip fluxing methods for very fine pitch and small bump sizes, vision recognition of the chip and substrate during assembly, reflowing of the flip chips on a wafer, and underfilling a solder balled WLCSP wafer with chip components in close proximity. Initial reliability results are presented which highlight that even though the flip chip is mounted silicon to silicon, the pitch and bump size make it so that the underfill selection has a large impact on the reliability of the assembly. Various aspects of the die to wafer assembly process are explored including scaling issues with high volume assembly, utilization of low cost underfill approaches such as no flow underfills and wafer applied underfills, and underfill encroachment on the WLCSP balls. Flux and underfill material combinations are identified that enable high assembly yields and provide reliable 3D-WLCSP assemblies with respect to liquid to liquid thermal shock testing and unbiased autoclave aging.

As mobile and handheld devices become more functionalities, required to accommodate more frequency bands, and to meet small form factor requirements. IPD (Integrated Passive Device) offers small form factor, and high performance benefits for RF solutions. To achieve a high performance RF filters, high-Q inductor is a key factor. A possible best high-Q inductor can be achieved is by Glass based solenoid inductor. In addition, 3D IPD process is another approach to reduce package size and increase functionality. In this paper, the fabrication process of IPD, based on 8 glass wafer with Through Glass Via (TGV) to form the 3D solenoid inductor is presented. In addition, the process integration between wafer level, assembly, and double-sided process are addressed. Along the process integration, a RF ASIC is integrated through wafer level and assembly process to form the 3D integrated Wafer Level Chip Scale Package (WLCSP). The quality factor of 3D solenoid inductors can achieve Q of 70~100 in this study. The TGV and package reliability results are also discussed.