A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE

In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

Power constraints are becoming a strong limiting factor in IC design. Lowering supply voltage is an appealing option to control power dissipation, but voltage scaling has a strong impact on performances. It is possible to design specific circuits for near- or even sub-threshold supply voltage, but many design environments cannot afford the development costs for libraries specifically designed and optimized for a sub-threshold regime. This work explores flow and design options for low-voltage targeting a standard library. After extending the library characterization to cover a low-voltage range, synthesis exploration has been performed on reference designs to assess the energy efficiency for different operating voltages/frequencies. The resulting netlists have been analyzed in terms of power dissipation and area after placement and routing. Results for two test cases show the available energy efficiency gain as well as the frequency range for which each reference supply voltage offers a convenient performance, and the design options impacting this choice. The energy efficiency obtained for two operating voltage configurations are compared against the reference designs, showing the different power/performance trade-offs achievable by scaling the supply voltage.

A New Two-Quadrant Squarer/Divider Circuit for true RMS-to-DC converters in MOS technology

A low voltage analog VLSI circuit model for Hodgkin–Huxley (HH) neuron cell equations (HH neuron model) is presented. Floating gate MOSFET (FGMOS) transistors in weak inversion region have been used to model HH equations such as gating variables, [Formula: see text] and [Formula: see text] functions and combined action of [Formula: see text], [Formula: see text] and [Formula: see text]. The combination of [Formula: see text], [Formula: see text] and [Formula: see text] controls the Na[Formula: see text] and K[Formula: see text] channel currents. The superiorities of the proposed circuits are low supply voltage, low power consumption, less circuit complexity and as a result, low costs are compared to the previous works. The proposed circuit which uses 24 transistors is simulated in Hspice software using 0.18[Formula: see text] technology and consumes 119[Formula: see text][Formula: see text]W.

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

The current conduction in polycrystalline silicon thin film transistors is analyzed in weak inversion, partially weak and strong inversion, and strong inversion regions. These operation regions can be determined from the dependence of the surface potential on the gate voltage under various channel potentials. In each different operation region, the source of the current conduction is analyzed based on the surface potential under the different channel potentials by some simple formulas. In comparison with other works and the calculated current components—the diffusion and drift current in the strong inversion, the current conduction is verified for both fully and partially depleted devices. It is found that the diffusion current dominates in the weak inversion region. Both diffusion and drift currents are important in the partially weak and strong inversion region. In the strong inversion region, the current conduction is determined by the drift component. It yields a new way to analyze the current conduction in polycrystalline silicon thin film transistors.

Bias non-conservation characteristics of high-frequency noise of 40nm n-MOSFETs are identified by measuring its drain current noise. Measurement results over a wide temperature range demonstrate the existence of thermal noise of 40nm n-MOSFETs in the weak and low middle inversion region, contrary to the predictions of suppressed shot noise model only suitable in the strong inversion and high middle inversion region. These new findings on the noise mechanisms of 40nm n-MOSFETs are very beneficial for its ultra low-voltage low-power RF application, such as noise analysis, circuit design and process technology evaluation.

An enhancement in the efficiency of an inverse Class F (Class $\text{F}^{-1})$ Doherty power amplifier (DPA) using a proposed triple-level supply modulator (SM) is presented. A three-level SM provides a lower supply voltage at a low input voltage, while providing the maximum level beyond the power back off. By adjusting the supply voltage in terms of the magnitude of the input signal, the efficiency of the main amplifier of the DPA over a wide input range is extended. For verification, a 2.4-GHz GaN Class $\text{F}^{-1}$ DPA was designed and fabricated. Using a 10 MHz 8.6 dB peak-to-average power ratio signal, at an average output power of 34.1 dBm, the fabricated Class $\text{F}^{-1}$ DPA achieves an efficiency level of 49%, which is 7.1% higher than that of a conventional amplifier. Under this condition, the measured adjacent channel leakage ratio (ACLR) is below −30 dBc.

This paper presents, a new configuration of linear CMOS subthreshold operational transconductance amplifier (LSOTA) working at 1.5 V with very low power consumption. Based on FGMOS technique, the developed OTA has a wide input range and small Gm, suitable for implementing low frequency analog and monolithic continuous-time filters. For demonstration a low pass second order filter was designed and simulated. The power consumption of the filter is less than 2 /spl mu/W and the topology achieves 76 dB linearity for fully balanced input dynamic range up to 1 Vpp at 1.5 V supply voltage.

A 1.2 V current-mode true RMS–DC converter based on the floating gate MOS translinear principle

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

Design and analysis of an adiabatic adder using Efficient Charge Recovery Logic is discussed. The study also presents the comparison of adiabatic adder with the CMOS logic-based adder. The power clock implementation for the adiabatic adder along with its characteristics have been studied. The performance of the new adiabatic adder counterparts is compared against the CMOS logic-based adders. The adders were simulated using Cadence Virtuoso 6.1.7 spectre simulator tool using 180 nm cmos technology for measurement of power dissipation, delay and PDP at 1.8V supply voltage and 200 MHz frequency. The adders were simulated at voltages ranging from 0.8V to 2.5V for power comparison. Simulation results dictate adiabatic adders can outperform the CMOS based adders in terms of power dissipation almost 45% less and requires lesser number of transistors.

In this paper, a current-mode automatic gain control (AGC) is presented. Due to operation in current-mode, the proposed circuit provides a wide frequency response, a low supply voltage, low power consumption and electronic controllability. Thus, it is very suitable for use in portable and battery-powered equipment such as hearing aid instrument and wireless radio device. The proposed AGC consists of current controlled exponential amplifier, current-mode precision rectifier, current-mode low pass filter and current-mode integrator. The performances of the proposed circuit are explored through HSPICE simulation program using BSIM3V3 model from MOSIS, they demonstrate good agreement to the theoretical anticipation. The proposed circuit works at /spl plusmn/1.5 V supply voltage, power consumption is merely 7.12mW.

An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(VGS - VT)2 even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.

A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18 mum CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.