FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

In this paper, a multi-input transconductance amplifier using Fully Differential Flipped Voltage Follower (FDFVF) has been proposed. The proposed circuit works at low supply voltage and produces large output current while using minimum number of active and passive elements. FVF technique has been used due to its differential characteristics along with low voltage and low power operation. Also proposed work realizes a high pass filter. The simulations of FDFVF based amplifier and its application in high pass filter has been shown using LTspice XVII.

A new wide input range square-rooting circuit is presented. The proposed circuit consists of a dual translinear loop, an absolute value circuit, and current mirrors. A current-mode technique is used to provide wide input range with simple circuitry. The output signal of the proposed circuit is the current which is proportional to the square root of input current. The proposed square-rooting circuit was confirmed by using PSpice simulator program. The simulation results demonstrate that the proposed circuit provides the excellent temperature stability with wide input current range.

An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(VGS - VT)2 even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.

An enhancement in the efficiency of an inverse Class F (Class $\text{F}^{-1})$ Doherty power amplifier (DPA) using a proposed triple-level supply modulator (SM) is presented. A three-level SM provides a lower supply voltage at a low input voltage, while providing the maximum level beyond the power back off. By adjusting the supply voltage in terms of the magnitude of the input signal, the efficiency of the main amplifier of the DPA over a wide input range is extended. For verification, a 2.4-GHz GaN Class $\text{F}^{-1}$ DPA was designed and fabricated. Using a 10 MHz 8.6 dB peak-to-average power ratio signal, at an average output power of 34.1 dBm, the fabricated Class $\text{F}^{-1}$ DPA achieves an efficiency level of 49%, which is 7.1% higher than that of a conventional amplifier. Under this condition, the measured adjacent channel leakage ratio (ACLR) is below −30 dBc.

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 mum CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of 0 plusmn1.5 dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.

This paper presents, a new configuration of linear CMOS subthreshold operational transconductance amplifier (LSOTA) working at 1.5 V with very low power consumption. Based on FGMOS technique, the developed OTA has a wide input range and small Gm, suitable for implementing low frequency analog and monolithic continuous-time filters. For demonstration a low pass second order filter was designed and simulated. The power consumption of the filter is less than 2 /spl mu/W and the topology achieves 76 dB linearity for fully balanced input dynamic range up to 1 Vpp at 1.5 V supply voltage.

Equivalence models (EM) advantages of neural networks (NN) are shown in paper. EMs are based on vectormatrix procedures with basic operations of continuous neurologic: normalized vector operations "equivalence", "nonequivalence", "autoequivalence", "autononequivalence". The capacity of NN on the basis of EM and of its modifications, including auto-and heteroassociative memories for 2D images, exceeds in several times quantity of neurons. Such neuroparadigms are very perspective for processing, recognition, storing large size and strongly correlated images. A family of "normalized equivalence-nonequivalence" neuro-fuzzy logic operations on the based of generalized operations fuzzy-negation, t-norm and s-norm is elaborated. A biologically motivated concept and time pulse encoding principles of continuous logic photocurrent reflexions and sample-storage devices with pulse-width photoconverters have allowed us to design generalized structures for realization of the family of normalized linear vector operations "equivalence"-"nonequivalence". Simulation results show, that processing time in such circuits does not exceed units of micro seconds. Circuits are simple, have low supply voltage (1-3 V), low power consumption (milliwatts), low levels of input signals (microwatts), integrated construction, satisfy the problem of interconnections and cascading.

A unique idea based on mixed-logic design for line decoder is designed by connecting transmission gate logic, pass transistor dual-value logic and static CMOS. Conventional techniques use static CMOS circuit to implement the design. However the power dissipation is observed to be high and the primary reason behind rise in power is due to increase in number of transistors. Here the proposed design uses mixed logic technique and GDI logic to build decoder which significantly decreases the transistor's count that results in low power consumption. Compared with mixed logic the GDI gives better result in power consumption and also delay reduction. Both normal and an inverting decoder designs are implemented. The proposed decoder can operate at low supply voltage and it finds its space in low power applications. Experimental results reveal that the proposed circuits present a significant improvement in terms of power, delay and transistor count and it outperforms the conventional CMOS based design.

The performance of the adder entirely influenced by the performance of its basic modules. In this paper, a new hybrid 1-bit 14 transistor full adder design is proposed. The proposed circuit has been implemented using pass gate as well as CMOS logic hence named hybrid. The main design objective for this circuit is low power consumption and full voltage swing at a low supply voltage. As a result the proposed adder cell remarkably improves the power consumption, power-delay product and has less parasitic capacitance when compared to the 16T design. It also improves layout area by 7–8 % than its peer design. All simulations are performed at 90 & 45 nm process technology on Synopsys tool.

A 9-bit ultra low-power successive approximation analog-to-digital converter (SA-ADC), which is able to operate at very low supply voltage, is presented. The low power consumption is achieved by using new switched-comparator architecture. In the proposed architecture the comparator, which is one of the most power hungry blocks of the SA-ADC, is switched off after the decision-making interval as well as during reset time to save power. The SA-ADC is simulated in the 0.18µm CMOS technology and the simulation results are provided. The switched-comparator SA-ADC consumes 412nW at 0.5V and as a result of the proposed switching scheme a power saving of 17.4% is obtained. It provides a signal-to-noise-and-distortion ratio (SNDR) of 50.36dB at the sampling rate of 12.5kS/s.

A 1mW 1.5 V 10-bit 500 KSPS successive approximation (SAR) analog-to-digital converter (ADC) was fabricated in a 0.25 um CMOS technology. The capacitive and resistive digital-to-analog converter (DAC) with a track and hold (T/H) function can operate with low power consumption at a high conversion rate using the modified operating timing control. The proposed high accuracy comparator with open loop and closed loop offset compensation techniques can operate at a low supply voltage. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are i 0.7 LSB and i 1.25 LSB, respectively. The total power consumption is 1 mW at a 500 KSPS conversion rate with a 1.5 V single supply voltage in measurement results.