Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx ISE 14.7 design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay by 34% and saves around 88% power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

Arithmetic and Logic Unit (ALU) is the most crucial and core component of central processing unit as well as of number of embedded systems and microprocessors. ALU consists of many computational units like adders, multipliers, logical units etc. Vedic Mathematics concepts are proposed here for designing the computational units of an 8-bit ALU. Here, a high-speed 8×8 bit multiplier is proposed which is based on the Vedic multiplier mechanism. A divider based on vedic mathematics is also proposed here. The proposed Vedic mathematics based ALU is designed using high level hardware description language – Verilog, followed by synthesization using EDA tool, Xilinx ISE 14.1. Finally, the synthesized circuit has been implemented on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) device.

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

Signal processing had a significant impact on the development of many elements of modern life, including telecommunications, education, healthcare, industry, and security. The semiconductor industry is the primary driver of signal processing innovation, producing ever-more sophisticated electronic devices and circuits in response to global demand. In addition, the central processing unit (CPU) is described as the “brain” of a computer or all electronic devices and signal processing. CPU is a critical electronic device that includes vital components such as memory, multiplier, adder, etc. Also, one of the essential components of the CPU is the arithmetic and logic unit (ALU), which executes the arithmetic and logical operations within all types of CPU operations, such as addition, multiplication, and subtraction. However, delay, occupied areas, and energy consumption are essential parameters in ALU circuits. Since the recent ALU designs experienced problems like high delay, high occupied area, and high energy consumption, implementing electronic circuits based on new technology can significantly boost the performance of entire signal processing devices, including microcontrollers, microprocessors, and printed devices, with high-speed and low occupied space. Quantum dot cellular automata (QCA) is an effective technology for implementing all electronic circuits and signal processing applications to solve these shortcomings. It is a transistor-less nanotechnology being explored as a successor to established technologies like CMOS and VLSI due to its ultra-low power dissipation, high device density, fast operating speed in THz, and reduced circuit complexity. This research proposes a ground-breaking ALU that upgrades electrical devices such as microcontrollers by applying cutting-edge QCA nanotechnology. The primary goal is to offer a novel ALU architecture that fully utilizes the potential of QCA nanotechnology. Using a new and efficient approach, the fundamental gates are skillfully utilized with a coplanar layout based on a single cell not rotated. Furthermore, this work presents an enhanced 1-bit and 2-bit arithmetic logic unit in quantum dot cellular automata. The recommended design includes logic, arithmetic operations, full adder (FA) design, and multiplexers. Using the powerful simulation tools QCADesigner, all proposed designs are evaluated and verified. The simulation outcomes indicates that the suggested ALU has 42.48 and 64.28% improvements concerning cell count and total occupied area in comparison to the best earlier single-layer and multi-layer designs.

An all-optical arithmetic and logic unit is the integral part of optical computing and data processing. In this paper, the author proposes a method to develop an all-optical arithmetic and logic unit by means of which so many binary logic operations such as AND, OR, NAND, NOR, EXOR, data comparator etc., as well as some arithmetic operations, such as half-addition, half-subtraction, full-addition, full-subtraction multiplication, etc., can be performed by properly selecting the frequencies of the control signals and using the frequency encoded input data. For this purpose, the author has exploited the frequency conversion scheme of semiconductor optical amplifier (SOA) using nonlinear polarization rotation character of the probe beam in SOA and, cross-gain modulation character of reflecting semiconductor optical amplifier (RSOA). Frequency-dependent optical beam routing to different channels have done using optical add/drop multiplexer made of SOA with multiquantum well structure. Frequency conversion efficiency of SOA and RSOA are very high as well as switching speed of SOA is very fast with very good ON-OFF contrast ratio.

Arithmetic and Logic Unit (ALU) is a combination circuit that performs a number of arithmetic and logical operations within a microprocessor.We present guidelines for low- and ultra low-power & high performance 32- bit ALU [1] units and analyze structures for logical operations to determine the most suitable for these regions of operations for low power applications.An ALU design is then modeled in VHDL for further testing with pre-manufactured parts of the 32 bit ALU using XILINX ISE tools. A novel method that chooses better designs of flipflops and latches in different places of the data path, based on the data and clock activities.Our simulation results indicate that, for the 180nm-65nm CMOS technologies [6] it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

A multiplier is the basic structural unit of many arithmetic logical units(ALU), digital signal processing(DSP) and communication system. So the area, speed and power consumption are the prime factors for the designing of multiplier circuits. QCA (Quantum dot-Cellular Automata) is one of the alternatives, which yields small size and low power consumption. In this paper, we proposed a 4-bit Vedic multiplier (using Urdhva Tiryagbhyam sutra) in QCA Technology. The generated partial product addition in Vedic multiplier is realized using carry-save technique. The design is simulated on QCA Designer tool and it confirms the efficiency of the design. The simulation result shows that, the proposed design has reduced 30% cell count, 60% reduction in area and 50% delay as compared to the 4×4 Wallace and Dadda multiplier.

Today's electronic circuits utilizes large amount of data and so have very high power dissipation. Usually, the overall system performance depends on the interconnection scheme and the individual processing element. The individual processing elements are the main workhorses of the system and hence are critical to the total performance of the system. Arithmetic and Logic Unit(ALU) is a widely used processing element. If the power dissipation of ALU can be reduced then overall power dissipation can be reduced and performance can be improved. In this paper one bit static ALU is implemented using static CMOS logic gates. Static AND and OR gates of static ALU is replaced by Data Driven Dynamic Logic(D 3 L) AND and OR gates to compare the power dissipation. The power dissipation, delay and PDAP was reduced when D 3 L AND and OR gates were used.

Multipliers are used in arithmetic and logic unit (ALU) and the performance of multiplier greatly depends on the number of adder cells. A study and performance investigation of array multiplier using low-power 10T full adder is presented. One of the crucial circuits in all digital devices is the adder cell and it is used in ALU. In this work, various performance parameters including power consumption, delay, and power-delay product are compared with full adder, array multiplier using 10T full-adder and static energy-recovery full (SERF) adder-based techniques. Array multipliers realized that using 10T-based full-adder circuit consumes less power when compared to SERF techniques. Simulation results show that the power consumption of array multiplier using 10T full-adder and SERF technique is 673.7 µW and 1.042 mW, respectively, which is less than the power consumption of conventional array multiplier. The power consumption and delay of proposed Array Multiplier are obtained using 180nm CMOS process.

Low power consumption is one of the leading design challenges while implementing any digital circuit. In platforms like wireless sensor networks where sensor nodes, located at various remote locations, are battery operated this challenge becomes more critical. Due to the lesser access to the deployment site, it is possible neither to change the battery nor to reconfigure the hardware to change the functionality of the deployed sensor node. Our approach of designing an ALU (Arithmetic and logic unit) with different arrangement and selection of elements than that conventionally used results in low power consumption (reduced by > 50%) without effecting the design complexity, total speed of operation and functionality. Additionally, the system is implemented on ZedBoard zynq evaluation and development kit so that the additional changes can be done on the hardware simply by modifying the HDL (Hardware description language) code.

Multipliers are the most important block in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the increasing constraints on delay, design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Among the sixteen sutras in Vedic multiplication techniques our proposed "URDHVA TIRYAKBHYAM" a most efficient technique in-terms of speed. In this project we aim at developing a multiplier using modified Adder which implements the "URDHVA TIRYAKBHYAM" sutra with improved speed of operation. Adders are vastly implemented in the critical path of many blocks of microprocessor chips. Our proposed adder is not only used for arithmetic logic units (ALUs). This adders are used in other parts of processor where they are used to calculate indices of table, corresponding condition and addresses. The efficiency of the digital system is greatly influenced by the performance of these adders. In this paper we proposed new innovative modified carry select adder with performance improvement in delay and area used. The most important parameters to be noted to measure the performance of adder designs are computation time and area. To compare results we have simulated types of adders in existing by using Xilinx tool and the results are compared.

Design of integrated reversible fault-tolerant arithmetic and logic unit

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.