A data and task parallel image processing environment for distributed memory systems

Developing embedded parallel image processing applications is usually a very hardware-dependent process, often using the single instruction multiple data (SIMD) paradigm, and requiring deep knowledge of the processors used. Furthermore, the application is tailored to a specific hardware platform, and if the chosen hardware does not meet the requirements, it must be rewritten for a new platform. We have proposed the use of design space exploration [9] to find the most suitable hardware platform for a certain application. This requires a hardware-independent program, and we use algorithmic skeletons [5] to achieve this, while exploiting the data parallelism inherent to low-level image processing. However, since different operations run best on different kinds of processors, we need to exploit task parallelism as well. This paper describes how we exploit task parallelism using an asynchronous remote procedure call (RPC) system, optimized for low-memory and sparsely connected systems such as smart cameras. It uses a futures [16]-like model to present a normal imperative C-interface to the user in which the skeleton calls are implicitly parallelized and pipelined. Simulation provides the task dependency graph and performance numbers for the mapping, which can be done at run time to facilitate data dependent branching. The result is an easy to program, platform independent framework which shields the user from the parallel implementation and mapping of his application, while efficiently utilizing on-chip memory and interconnect bandwidth.

The aim of digital image processing is to improve the quality of image and subsequently to perform features extraction and classification. It is effectively used in computer vision, medical imaging, meteorology, astronomy, remote sensing and other related field. The main problem is that it is generally time consuming process; Parallel Computing provides an efficient and convenient way to address this issue. Main purpose of this review is to provide the comparative study of the existing contributions of implementing parallel image processing applications with their benefits and limitations. Another important aspect of this study is to provide the brief introduction of parallel computing and currently available parallel architecture, tools and techniques used for implementing parallel image processing. The aim is to discuss the problems encountered to implement parallel computing in various image processing applications. In this research we also tried to describe the role of parallel image processing in the field of medical imaging.

The paper presents an approach of using algorithmic skeletons for adding data parallelism to an image processing library. The method is used for parallelizing image processing applications composed of low-level image operators on a distributed memory system. In this way, a user who wants to parallelize an image processing application is not involved in the design and the implementation of parallel algorithms, but his only task is how to select for each low-level operator the appropriate skeleton to obtain the parallel version of the application. Example of the multibaseline stereo vision image processing aplication is given for reference.

Analysis of a model for parallel image processing

This paper reports on the integration of parallel image processing in the ITK library and on improvements to the state-of-the-art of user transparency. In our approach, image processing tasks are wrapped into objects which are passed to the parallel engine. The engine is able to exploit data and task parallelism when executing the tasks on multicores, clusters and/or GPUs. All features necessary for efficient parallel processing are specified by the task objects. The engine can figure out most of the features itself, and is able to check the correctness of the features provided by the user. Interoperation optimization is attained by efficient scheduling of the tasks. The task dependency graph is automatically created at runtime. This is possible by delaying the execution of the tasks and by the intrinsic ITK pipeline updating mechanism. The low-level functions are also made available for the user, as well as a library-independent version.

The paper presents a method to integrate parallelism in the DIPLIB sequential image processing library. The library contains several framework functions for different types of operations. We parallelize the filter framework function (contains the neighborhood image processing operators). We validate our method by testing it with the geometric mean filter. Experiments on a cluster of workstations show linear speedup.

In this paper we present a two-dimensional cellular hypercube architecture for image processing that combines features of the conventional hypercube and cellular logic architectures for 2-D computation cells. A unified theory of parallel binary image processing, binary image algebra (BIA), serves as a software tool for designing parallel image processing algorithms. To match the hardware to the software, we characterize the cellular processors using the same algebraic structure as BIA. The two-dimensional cellular hypercube image processor is a cellular SIMD machine with N2 cells and has a simple overall organization, low cell complexity and fast processing ability. An optical cellular hypercube implementation of BIA is proposed which offers parallel input/output and global interconnection capabilities which are difficult to do in planar VLSI technology.

Massively deployed inside Sony PS3 platforms, the STI Cell Broadband Engine is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). In this paper, we describe three image processing applications which we implemented on the Cell BE. We report the performance measured on one Cell blade with varying numbers of synergic processor engines enabled, and with varying application parameters. These results were compared to the results obtained on the Cell BE running a single PPE and with all 8 SPEs disabled. The results reveal the superior performance of image processing and SIMD-prone applications on the 9-core Cell BE processor over conventional RISC processors.

A great number of parallel computer architectures have been proposed, whether they are SIMD machines (Single Instruction Multiple Data) with lots of quite simple processors, or MIMD machines (Multiple Instruction Multiple Data) containing few, but powerful processors. Each one claims to offer some kind of an optimality at the hardware level. But implementing parallel image processing algorithms to make them run in real time will remain a real challenge; it addresses rather the control of communication networks between processors (message passing, circuit switching..) or the computing model (e.g. data parallel model). In that respect, our goal here is to point out some algorithmic needs to distribute image processing operators. They will be translated first in terms of programming models, more general then image processing applications, and then as hardware properties of the processor network. In that way, we do not design yet another parallel machine dedicated to image processing, but a more general parallel architecture which one will be able to efficiently implement different kinds of programming models.

Directly performing optical analog computations and image processing in space, such as optical differential operations and image edge detection, is a burgeoning area. To avoid the bulkiness and low efficiency of traditional 4 f filtering systems, one can utilize Green's function and metasurfaces for advanced wavefront control. However, some metasurface differentiators can be hindered by issues like polarization sensitivity, restricted bandwidth, low resolution, and the need for additional polarization devices or digital post‐processing, potentially degrading their performance and operation efficiency. In this work, a dual‐polarization Laplace differentiator is engineered to address these issues based on nonlocal hollow metasurface. The optical transfer function (OTF) required by the Laplace operation can be obtained by exciting different quasi‐bound states in the continuum (Q‐BIC) modes with distinct angular dispersion capabilities under p ‐ and s ‐polarized illumination, respectively. This Laplace differentiator not only directly realizes 2D second‐order edge detection in a dual‐polarization channel but also features a numerical aperture (NA) with an upper limit close to 0.42 and a broadband range reaching 165 nm. Such an efficient, high‐quality dual‐polarization and bandwidth image edge detection approach offers powerful imaging techniques for applications in machine vision, microscopic imaging, and image processing.

This paper provides a tutorial on the motivations, design, and applications of parallel processing applied to video real-time, illustrated by the experience gained in the implementation of the P/sup 3/I machine. Its main purpose is to highlight the motivations for such a development the basic implementation choices, the major difficulties encountered and how they have been solved. Through these studies we found that parallel processing is well-suited to video real-time, when programmable implementations are considered. There are many outcomes of the P/sup 3/I project, ranging from architectural considerations to parallel algorithms optimizations, and programming methodology. We want to emphasize three conclusions. First, programming an architecture composed of different parallel paradigms in a given architecture is tractable, and this heterogeneity is cost effective and efficient in terms of processing performances. Second, concerning the well known debate about how to match parallel architectures and image processing "levels" we conclude that the key is not to discuss Flynn's taxonomy (i.e., data versus tasks parallelism) but to consider how the parallelism grain evolves within a whole application. Third, we confirm that in the field of image processing, the efficiency of parallelism can only be gained if algorithms developers think "parallel"; this result seems to be obvious, but just consider the trends of recent RISC processors, embedding more and more parallelism, and claiming at a compatibility with existing sequential softwares.

. The development of an Image Processing (IP) application is a complex activity, which can be greatly alleviated by user-friendly graphical programming environments. Our major objective is to help IP experts reuse parts of their applications. A first work towards knowledge reuse has been to propose a suitable representation of the strategies of IP experts by means of IP plans (trees of tasks, methods and tools). This paper describes the CBR module of our interactive system for the development of IP plans. After a brief presentation of the overall architecture of the system and its other modules, we explain the distinction between an IP case and an IP plan, and give the selection criteria and functions that are used for similarity calculation. The core of the CBR module is a search/adaptation algorithm, whose main steps are detailed: retrieval of suitable cases, recursive adaptation of the selected one and memorization of new cases. The system’s implementation is presently completed; its functioning is described in a session showing the kind of assistance provided by the CBR module during the development of a new IP application.

In order to speedup image processing in embedded environment, we construct a parallel processing system of images. The parallel processing system includes a parallel hardware, a new defined language for parallel image processing and a set of software tools. From the view of high performance, low power dissipation and the characteristics of image processing, we construct a SIMD coprocessor as an image processing accelerator. Using a RISC host processor manages the whole system. The SIMD processor is scalable. We also define a new language which is extended from standard C. A new data type and a new keyword kernel are added to the language to explicitly describe parallelism. For the new hardware and language of parallel image processing, we also research software tools for this parallel system. The software tools maps programs to code that runs on the new hardware. For example develop a scheduler to transfer stream data between memories and register files. From the analysis we found that the parallel image processing system can not only match image applications' characteristics but also easy to implement by using VLSI technology. With new language and software tools supporting, an embedded real-time parallel image processing system becomes available for programmers.

This paper introduces the modular cellular neural network (CNN), which is a new CNN structure constructed from nine one-layer modules with intercellular interactions between different modules. The new network is suitable for implementing many image processing operations. Inputting an image into the modules results in nine outputs. The topographic characteristic of the cell interactions allows the outputs to introduce new properties for image processing tasks. The stability of the system is proven and the performance is evaluated in several image processing applications. Experiment results on texture segmentation show the power of the proposed structure. The performance of the structure in a real edge detection application using the Berkeley dataset BSDS300 is also evaluated.

Algorithmic skeletons can be used to write architecture independent programs, shielding application developers from the details of a parallel implementation. In this paper, we present a C-like skeleton implementation language, PEPCI, that uses term rewriting and partial evaluation to specify skeletons for parallel C dialects. By using skeletons to control the iteration of kernel functions, we provide a stream programming language that is better tailored to the user as well as the underlying architecture. Skeleton merging allows us to reduce the overheads usually associated with breaking an application into small kernels. We have implemented an example image processing application on a heterogeneous embedded prototype platform consisting of an SIMD and ILP processor, and show that a significant speedup can be achieved without requiring knowledge of data parallel processing.