Analysis of a model for parallel image processing

The aim of digital image processing is to improve the quality of image and subsequently to perform features extraction and classification. It is effectively used in computer vision, medical imaging, meteorology, astronomy, remote sensing and other related field. The main problem is that it is generally time consuming process; Parallel Computing provides an efficient and convenient way to address this issue. Main purpose of this review is to provide the comparative study of the existing contributions of implementing parallel image processing applications with their benefits and limitations. Another important aspect of this study is to provide the brief introduction of parallel computing and currently available parallel architecture, tools and techniques used for implementing parallel image processing. The aim is to discuss the problems encountered to implement parallel computing in various image processing applications. In this research we also tried to describe the role of parallel image processing in the field of medical imaging.

This paper provides a tutorial on the motivations, design, and applications of parallel processing applied to video real-time, illustrated by the experience gained in the implementation of the P/sup 3/I machine. Its main purpose is to highlight the motivations for such a development the basic implementation choices, the major difficulties encountered and how they have been solved. Through these studies we found that parallel processing is well-suited to video real-time, when programmable implementations are considered. There are many outcomes of the P/sup 3/I project, ranging from architectural considerations to parallel algorithms optimizations, and programming methodology. We want to emphasize three conclusions. First, programming an architecture composed of different parallel paradigms in a given architecture is tractable, and this heterogeneity is cost effective and efficient in terms of processing performances. Second, concerning the well known debate about how to match parallel architectures and image processing "levels" we conclude that the key is not to discuss Flynn's taxonomy (i.e., data versus tasks parallelism) but to consider how the parallelism grain evolves within a whole application. Third, we confirm that in the field of image processing, the efficiency of parallelism can only be gained if algorithms developers think "parallel"; this result seems to be obvious, but just consider the trends of recent RISC processors, embedding more and more parallelism, and claiming at a compatibility with existing sequential softwares.

We have designed and constructed a column parallel vision (CPV) system to realize an intelligent and general purpose image processing system with higher frame rate within 1 millisecond. The system consists of an original designed photo detector array (PDA) with high frame rate, a parallel processing unit with fully parallel processing elements (PEs), and a controller for PDA and PEs. The column parallel architecture enables the PDA 1 millisecond frame rate with 256 analog levels which is required for industrial image processing and measurements. The parallel processing unit has been fabricated by using FPGAs and has 128 X 128 PEs to perform the fully parallel image processing. The PEs have the S<SUP>3</SUP>PE architecture which has SIMD type parallel processing flow, and was constructed only 500 transistors suitable for integration in future. Since the PEs are operated by control signal from the controller, we can achieve desired image processing task to the system by changing the software. We have demonstrated that the system can be worked as a tracking system. The experimental results show the system was realized high speed feedback loop as 1000 frame/s including the tracking operation with noise reduction, matching (self-window algorithm) and moment calculation.

In this paper we present a two-dimensional cellular hypercube architecture for image processing that combines features of the conventional hypercube and cellular logic architectures for 2-D computation cells. A unified theory of parallel binary image processing, binary image algebra (BIA), serves as a software tool for designing parallel image processing algorithms. To match the hardware to the software, we characterize the cellular processors using the same algebraic structure as BIA. The two-dimensional cellular hypercube image processor is a cellular SIMD machine with N2 cells and has a simple overall organization, low cell complexity and fast processing ability. An optical cellular hypercube implementation of BIA is proposed which offers parallel input/output and global interconnection capabilities which are difficult to do in planar VLSI technology.

The problem addressed is how to use transputer networks for image processing. As is well known, SIMD (single instruction/multiple data) or MIMD (multiple instruction/multiple data) architectures are very useful in parallel computing. The authors describe how to use transputers as a SIMD or MIMD machine to implement parallel image processing. Several image-processing algorithms, including Laplacian of Gaussian, edge detection, region labeling, generalized Hough transform, and thinning, have been tested. The authors maintain that transputer-based systems are suitable for real-time image processing. It is also pointed out that, compared with the other parallel machines, transputer systems can provide high performance and more flexibility with relatively low cost. >

A massively parallel signal and image processing architecture is considered. The architecture is comprised of 2D arrays of cells that simulate the response of retina neurons. The results of simulations are compared to previously published experimental results and the system is applied to detection of spatio-temporal features in sequences of images representative of pulse- doppler radar images. By arranging the output layer so that the cells respond to various key input features an array of feature extraction cells can be obtained. The system is characterized by developing an image space to feature space mapping.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A great number of parallel computer architectures have been proposed, whether they are SIMD machines (Single Instruction Multiple Data) with lots of quite simple processors, or MIMD machines (Multiple Instruction Multiple Data) containing few, but powerful processors. Each one claims to offer some kind of an optimality at the hardware level. But implementing parallel image processing algorithms to make them run in real time will remain a real challenge; it addresses rather the control of communication networks between processors (message passing, circuit switching..) or the computing model (e.g. data parallel model). In that respect, our goal here is to point out some algorithmic needs to distribute image processing operators. They will be translated first in terms of programming models, more general then image processing applications, and then as hardware properties of the processor network. In that way, we do not design yet another parallel machine dedicated to image processing, but a more general parallel architecture which one will be able to efficiently implement different kinds of programming models.

The paper describes the design concept and the implementation of the imaging database, Online Image Delivery System (OLIDS). We propose a new framework to support vertically parallel image processing in multimedia database systems. We present a generic and customizable framework for specifying an image query execution plan that permits the DBMS to optimize and execute parallel image processing. Moreover, it is important to provide the multimedia applications with the capability for customizing the information server according to specific requirements. This customization capability also provides both challenges and opportunities in building high performance multimedia and image systems. Applications such as Active hypermedia project or MODOS (Museum project between LRMF (France), NMWA and NACSIS (Japan)) demonstrate the usefulness of the customizable feature of the application oriented DBMS, Phasme, a microkernel database system, tested and extended inside NACSIS.

An FPGA Based SIMD Architecture Implemented with 2D Systolic Architecture for Image Processing

With the rapid development of microelectronics technology, digital image processing technology has deepened our lives. In the past, image processing mostly used software processing. Due to the large number of processing algorithms and the complexity of the algorithm, it could not meet the real-time requirements. Therefore, this paper proposes a method for parallel processing of ultrasound images based on fax by using a programmable logic device. Image fusion is to extract and synthesize complementary information from different sensors to obtain a more accurate, comprehensive and reliable description of the target or scene. The transmission of images and other images is achieved by the sound of various sensors, which is far from enough. This article presents the use of hardware description language to design image processing and drivers. The core of the print head, scan head and stepper motor can use the control interface to perform selective and parameter variable median filtering on the scanned graphic image through software. Edge sharpening, image field separation, binarization and other hardware processing are compared with a series of processing directly using software, and the optimal processing plan can be made well, and the processed image can be displayed and printed out on the. This design can produce practical results for designs in the fields of biomedicine, sports, and energy production.

The paper presents a data and task parallel low-level image processing environment for distributed memory systems. Image processing operators are parallelized by data decomposition using algorithmic skeletons. At the application level we use task decomposition, based on the Image Application Task Graph. In this way, an image processing application can be parallelized both by data and task decomposition, and thus better speed-ups can be obtained. We validate our method on the multi-baseline stereo vision application.

In order to speedup image processing in embedded environment, we construct a parallel processing system of images. The parallel processing system includes a parallel hardware, a new defined language for parallel image processing and a set of software tools. From the view of high performance, low power dissipation and the characteristics of image processing, we construct a SIMD coprocessor as an image processing accelerator. Using a RISC host processor manages the whole system. The SIMD processor is scalable. We also define a new language which is extended from standard C. A new data type and a new keyword kernel are added to the language to explicitly describe parallelism. For the new hardware and language of parallel image processing, we also research software tools for this parallel system. The software tools maps programs to code that runs on the new hardware. For example develop a scheduler to transfer stream data between memories and register files. From the analysis we found that the parallel image processing system can not only match image applications' characteristics but also easy to implement by using VLSI technology. With new language and software tools supporting, an embedded real-time parallel image processing system becomes available for programmers.

Developing embedded parallel image processing applications is usually a very hardware-dependent process, often using the single instruction multiple data (SIMD) paradigm, and requiring deep knowledge of the processors used. Furthermore, the application is tailored to a specific hardware platform, and if the chosen hardware does not meet the requirements, it must be rewritten for a new platform. We have proposed the use of design space exploration [9] to find the most suitable hardware platform for a certain application. This requires a hardware-independent program, and we use algorithmic skeletons [5] to achieve this, while exploiting the data parallelism inherent to low-level image processing. However, since different operations run best on different kinds of processors, we need to exploit task parallelism as well. This paper describes how we exploit task parallelism using an asynchronous remote procedure call (RPC) system, optimized for low-memory and sparsely connected systems such as smart cameras. It uses a futures [16]-like model to present a normal imperative C-interface to the user in which the skeleton calls are implicitly parallelized and pipelined. Simulation provides the task dependency graph and performance numbers for the mapping, which can be done at run time to facilitate data dependent branching. The result is an easy to program, platform independent framework which shields the user from the parallel implementation and mapping of his application, while efficiently utilizing on-chip memory and interconnect bandwidth.

As systems become more complex, particularly those containing embedded decision algorithms, mathematical modeling presents a rigid framework that often impedes representation to a sufficient level of detail. Using discrete event simulation, one can build models that more closely represent physical reality, with actual algorithms incorporated in the simulations. Higher levels of detail increase simulation run time. Hardware designers have succeeded in producing parallel and distributed processor computers with theoretical speeds well into the teraflop range. However, the practical use of these machines on all but some very special problems is extremely limited. The inability to use this power is due to great difficulties encountered when trying to translate real world problems into software that makes effective use of highly parallel machines. This paper addresses the application of parallel processing to simulations of real world systems of varying inherent parallelism. It provides a brief background in modeling and simulation validity and describes a parameter that can be used in discrete event simulation to vary opportunities for parallel processing at the expense of absolute time synchronization and is constrained by validity. It focuses on the effects of model architecture, run-time software architecture, and parallel processor architecture on speed, while providing an environment where modelers can achieve sufficient model accuracy to produce valid simulation results. It describes an approach to simulation development that captures subject area expert knowledge to leverage inherent parallelism in systems in the following ways: * Data structures are separated from instructions to track which instruction sets share what data. This is used to determine independence and thus the potential for concurrent processing at run-time. * Model connectivity (independence) can be inspected visually to determine if the inherent parallelism of a physical system is properly represented. Models need not be changed to move from a single processor to parallel processor hardware architectures. * Knowledge of the architectural parallelism is stored within the system and used during run time to allocate processors to processes in a maximally efficient way.

Echo data generated by Synthetic aperture radar (SAR) has the characteristics of high data rate and huge data quantity. However, the complex Chirp Scaling (CS) algorithm in SAR processing leads to excessive calculations. To solve this problem, this paper presents an implementation on a parallel structure real-time image processing board, which adopts principal-subordinate parallel processing structures. The principal FPGA board is responsible for the control of the entire image processing, data collection, distribution and interaction. Each subordinate FPGA, as an independent processing unit, is able to independently finish the FFT transformation and phase factor compensation. The performance of the high-performance parallel FFT processors is 4 times as efficient as that of a single butterfly processor.The phase factor generation and compensation is optimized through two steps, one is fast algorithm in phase factor generation and compensation; the other is the optimization among the processing procedures,The proposed architecture can process an image in size16384 × 65536 at 100MHZ operation frequency within 12.5s.