A Defect-Detection Graph-Based Methodology for Cell-Aware Model Generation

A novel magnetic field image (MFI) solver is developed for defect localization in 3-dimensional (3D) Integrated Circuit (IC) packages. The 2-dimensional (2D) data array of magnetic field measurements are first convolved with Ramanujan sums to obtain a pair of defect clusters that represent the fundamental period of the data. The clusters are then correlated through Mahalanobis distance from which defect coordinates in the three cartesian axes are precisely determined. Analysis with data from a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2. 5 D}$</tex> graphics processing unit (GPU), which includes a Silicon interposer, high bandwidth memory (HBM) modules, and an application specific integrated circuit (ASIC) processor, containing an electrical short circuit defect, reveals a 57 % improvement in Z-height localization accuracy, a 30 % increase in noise tolerance, and a 33 % reduction in computation time, as compared to state-of-the-art iterative 3D current solver. The solver offers best-in-class iteration-free fault localization and diagnosis capability for next generation 3D-IC packages.

Specific energy consumption of dynamic random access memory module supply chain in Taiwan

Integrated circuit (IC) applications have become viable, reliable, and cheaper with deep-submicron technologies in VLSI industry. SoC (system on chip) is a microchip, which holds the necessary hardware and software to implement various functions onto a single chip. An IC should be tested during design process to check the correctness of the design and also to check the functionality of the design after fabrication. Testing cost shares almost half of the manufacturing expenditure. Achieving high-test quality in reduced VLSI geometry increases the complexity of the testing methods because of huge volume of test data. Automatic testing equipment (ATE) reduces testing efforts, but it has limited memory in comparison with the huge volume of the test data. One of the methods to reduce the burden of ATE is test data compression. The advantages of test data compression are as follows: (i) reduction in memory requirement for ATE and (ii) reduction in testing time. Though many advanced algorithms are used for testing of VLSI circuits, most of them are expensive in terms of test data volume and power. This survey discusses all the test data compression methods, and it helps the researchers in testing domain.

Side-channel attacks (SCAs) pose a threat to cryptographic security by potentially recovering secret keys through the analysis of radio-frequency switching noise emitted from cryptographic integrated circuits (ICs). Predicting tolerance for SCAs enables the implementation of countermeasures in the short term. To enable fast prediction, we model the switching current transferred from the IC to the power distribution network (PDN) as a triangular pulse, subsequently applying multiple regression analysis to this pulse. As in our previous paper, we approximate the triangular pulse using register transfer level (RTL) logic simulations, which facilitate a faster prediction of the current. By applying multiple regression analysis, we can predict the SCA tolerance using a few current waveforms. To validate our model, we predicted the switching current for a field programmable gate array (FPGA) implementing the advanced encryption standard (AES) circuit, converted this into PDN noise, and then performed a primary SCA method called correlation power analysis (CPA). The results show that our method can predict PDN noise and SCA tolerance with more than a 90 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> reduction in analysis time compared to the previous method.

During fabrication process, mixed analog and digital integrated circuits (ICs) are more susceptible to process variations and physical defects than pure digital ICs. Therefore, it is beneficial to simulate the effects of process variations and defects on mixed-signal designs even before the design goes into production. Simulations of ICs having process variations are performed with Monte Carlo simulations. And, simulations of ICs having physical defects are called fault simulations. However, both simulation schemes require large numbers of instances. Consequently, simulation times can be extremely long, e.g. hours or days. In this System-on-a-Chip (SoC) era, mixed-signal designs are becoming more complex and thus impossible for traditional simulation schemes to be effectively applied. To dramatically reduce Monte Carlo simulation time and fault simulation time, a new behavioral simulation approach is proposed in this dissertation. Essentially, timing consuming detailed circuit simulations can be replaced by simple linear equations. A flash analog-to-digital converter (ADC) is used here to demonstrate the feasibility of proposed approach. The behavioral models for the flash ADC having process variations and physical defects are built. With these behavioral models, behavioral simulation programs are written in C++ to perform fast Monte Carlo simulations and fault simulations. For the small 3-bit flash ADC, the proposed method reduced the Monte Carlo simulation time, with 30 instances, from 180 hours to a mere 15 minutes. Such dramatic reduction in simulation time was achieved with a maximum prediction error of no more than 6%.

Silicon microphotonics is the optical equivalent of microelectronics for integrated circuits. Photonics enables interconnection that is not limited by transmission bandwidth. Photonic switching promises ultrafast routing and encoding of information for telecommunications and data transmission. The key implementation issue is the integration of photonic components with integrated circuit electronics. Silicon microphotonics utilizes silicon-based materials that are process compatible with standard integrated circuit fabrication methods.

Standard cell libraries are an important part of many of today's integrated circuit (IC) designs. The design of all digital ASICs (Application Specific Integrated Circuit) essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s. In this paper the work involves, designing standard cell layouts with different cells using fixed height of standard cell template and characterizing standard cells using liberate and generating. lib file for standard cell. This Standard cell library was designed an industry academia chip collaborative project. By using Cadence virtuoso, liberate tools high performance with low power consumption standard cell library was developed.

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

Current trends in computing require dedicated chips to speed up computing performances. These dedicated chips or ASICs are designed for specific applications, however, the drawback in this approach is that IC (Integrated Circuits) functionality cannot be changed. In areas where H/W programmability and reconfigurability is required, FPGA is the solution to achieve this. System on Chip (SOC) FPGAs (Field Programmable Gate Arrays) include processor hard blocks connected to fabric through various interconnects. This architecture provides better performance and the ability to run Operating Systems (OS) like Linux <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> that has direct access to programmable FPGA logic. This paper explains how to split the functions of an application code between hard block processor and FPGA fabric logic. OPUS is an open-source audio codec widely used in voice-over-IP (VoiP) applications. The codec execution can be accelerated by moving some of its functions to FPGA logic. One such function of OPUS code is implemented in FPGA logic using High-Level Synthesis (HLS). Shared DDR memory space is used to transfer the data between the processor and FPGA. In this paper, we summarize the reduction in execution time and processor load. The acceleration of OPUS codec allows processing of a greater number of audio channels in the SoC device compared to running the codec entirely on the processor.

The nano-scale 3-D interconnects available in monolithic 3-D integrated circuit (IC) technology enable ultrahigh density device integration at the individual transistor level. In this paper, we investigate the benefits and challenges of monolithic 3-D integration technology for ultrahigh density logic designs. We first build a 3-D standard cell library for transistor-level monolithic 3-D ICs and model their timing and power characteristics. Then, we explore various interconnect options for monolithic 3-D ICs that improve design quality. Next, we build timing-closed, full-chip GDSII layouts and perform sign-off iso-performance power comparisons with 2-D IC designs. Based on layout simulations, we compare important design metrics such as area, wirelength, timing, and power consumption of transistor-level monolithic 3-D designs with traditional 2-D, gate-level monolithic 3-D, and TSV-based 3-D designs.

Integrated circuit aging effects are more and more pronounced with the continuous technological downscaling. These effects degrade circuit operation which is mainly observed as increased input-to-output delay of circuit components. Eventually, the circuit falls out of its specifications. Countermeasures are needed to prevent or reduce such degradation. Aging monitoring can be very beneficial since it can predict circuit failure and/or activate mechanisms to avoid failure. Most of the present aging monitors are based on reporting abnormal input-to-output signal delays on the critical path of the circuit. However, present approaches introduce additional circuit complexity, use complicated analog design, use non-standard cells etc. We propose a low-complexity aging monitor based on standard library cells, offering simplicity and flexibility of its design, integration and use. The designer could instantiate many monitors throughout the integrated circuit. The user can simply read the “aging code” placed in a register in each monitor and determine the “age” of the circuit, predict a circuit failure and/or take an appropriate action. This is especially useful in microprocessors which are designed with dependability in mind.

Lack of rapid and comprehensive microbiological diagnosis in patients with community acquired pneumonia (CAP) hampers appropriate antimicrobial therapy. This study evaluates the real-world performance of the BioFire FilmArray Pneumonia panel plus (FAP plus) and explores the feasibility of evaluation in a randomised controlled trial. Patients presenting to hospital with suspected CAP were recruited in a prospective feasibility study. An induced sputum or an endotracheal aspirate was obtained from all participants. The FAP plus turnaround time (TAT) and microbiological yield were compared with standard diagnostic methods (SDs). 96/104 (92%) enrolled patients had a respiratory tract infection (RTI); 72 CAP and 24 other RTIs. Median TAT was shorter for the FAP plus, compared with in-house PCR (2.6 vs 24.1 h, p < 0.001) and sputum cultures (2.6 vs 57.5 h, p < 0.001). The total microbiological yield by the FAP plus was higher compared to SDs (91% (162/179) vs 55% (99/179), p < 0.0001). Haemophilus influenzae, Streptococcus pneumoniae and influenza A virus were the most frequent pathogens. In conclusion, molecular panel testing in adults with CAP was associated with a significant reduction in time to actionable results and increased microbiological yield. The impact on antibiotic use and patient outcome should be assessed in randomised controlled trials.

Classical active flow control (AFC) methods based on solving the Navier–Stokes equations are laborious and computationally intensive even with the use of reduced-order models. Data-driven methods offer a promising alternative for AFC, and they have been applied successfully to reduce the drag of two-dimensional bluff bodies, such as a circular cylinder, using deep reinforcement-learning (DRL) paradigms. However, due to the onset of weak turbulence in the wake, the standard DRL method tends to result in large fluctuations in the unsteady forces acting on the cylinder as the Reynolds number increases. In this study, a Markov decision process (MDP) with time delays is introduced to model and quantify the action delays in the environment in a DRL process due to the time difference between control actuation and flow response along with the use of a first-order autoregressive policy (ARP). This hybrid DRL method is applied to control the vortex-shedding process from a two-dimensional circular cylinder using four synthetic jet actuators at a freestream Reynolds number of 400. This method has yielded a stable and coherent control, which results in a steadier and more elongated vortex formation zone behind the cylinder, hence, a much weaker vortex-shedding process and less fluctuating lift and drag forces. Compared to the standard DRL method, this method utilizes the historical samples without additional sampling in training, and it is capable of reducing the magnitude of drag and lift fluctuations by approximately 90% while achieving a similar level of drag reduction in the deterministic control at the same actuation frequency. This study demonstrates the necessity of including a physics-informed delay and regressive nature in the MDP and the benefits of introducing ARPs to achieve a robust and temporal-coherent control of unsteady forces in active flow control.

As semiconductor content penetrates deeper into our everyday lives, the quality of the electronic components that surrounds us becomes ever more important, particularly for those involved in safety-critical applications such as automated vehicles and healthcare. For integrated circuits (IC), cell-aware testing (CAT) is the latest advancement in the drive towards zero end-user defects. CAT targets physical defects such as bridges and opens at the transistor level inside standard logic cells used to construct the IC. A fairly onerous process involving extensive analog simulation is used to characterize cell behavior in the presence of defects, and create fault models to guide the generation of chip-level test patterns that can detect these physical defects. Assuming use of a single analog simulator license, cell-aware fault modeling (CAFM) for a library of standard cells can take up to weeks to months of computation. Moreover, for certain types of defects, stand-alone library-based CAFM fails to account for strong interactions with the cell's surrounding design context on an instance basis. As a result, the created fault model may fall short in generating the optimal chip-level test patterns for defect detection and accurate failure diagnosis. In this talk, we propose the idea of "in-situ" CAFM to properly account for cell instance design context. To realize in-situ CAFM in practice, drastic improvements in efficiency and performance of the characterization process is needed. We show how a transistor switch-based approach involving switch-level fault proxies and test generation can achieve the required performance gain by eliminating much unnecessary analog simulation. Early experimental data demonstrates CAFM can be improved by two orders-of-magnitude using our approach.

As the speed of railway transportation grows rapidly, welded structures have been commonly used for the car bodies and bogies. Fatigue failure of a welded structure with fluctuating loads usually occurs at weld seams. And thus the fatigue strength of weld seams should be considered in the optimization of these structures. In this paper, an adaptive multidisciplinary optimization method is proposed for the lightweight optimization problem with weld fatigue constraints. The kriging surrogate models are used to replace the time-consuming computer simulations through the optimization procedure. The master S–N curve method in ASME standard is adopted for weld fatigue assessment due to its mesh-insensitivity and reliability. For a brake beam structure of a high-speed train, a lightweight optimization model with static strength and weld fatigue constraints is constructed and solved in light of the proposed optimization method. After optimization, the weight of the brake beam is reduced by 12.5% and the values of weld fatigue damage meet the requirements, which demonstrate the validity of the proposed optimization method. Furthermore, an optimization without weld fatigue constraints is implemented and the optimal design leads to unacceptable values of weld fatigue damage. This shows that the weld fatigue problems cannot be ignored in the optimization for welded structures.