Test Data Compression Methods: A Review

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

The low throughput at IC (integrated circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (automatic test equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (multiple-input signature register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).

This paper presents a comprehensive hybrid test vector compression method for very large scale integration (VLSI) circuit testing, targeting specifically embedded cores-based system-on-chips (SoCs). In the proposed approach, a software program is loaded into the on-chip processor memory along with the compressed test data sets. To minimize on-chip storage besides testing time, the test data volume is first reduced by compaction in a hybrid manner before downloading into the processor. The method uses a set of adaptive coding techniques for realizing lossless compression. The compaction program need not to be loaded into the embedded processor, as only the decompression of test data is required for the automatic test equipment (ATE). The developed scheme necessitates minimal hardware overhead, while the on-chip embedded processor can be reused for normal operation on completion of testing. This paper reports results on studies of the problem and demonstrates the feasibility of the suggested methodology with simulation runs on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits.

Network-on-chip (NoC) has been proposed as a scalable communication infrastructure to establish connections between integrated cores which are increased on a single chip. NoC structure consisting of components and elements such as routers, processing elements and links that can be error prone. Therefore, to achieve the correct functioning of a network, test operation has been a major concern for chip designers. In offline test mechanism, the distance between test pattern generator and destinations has significant impact on the test time. Using multicast scheme, this paper proposed a new mechanism that tests all cores. Our proposed approach first divides the network to four parts and then locates one ATE with four ports in the middle of the network. Based on our method, test operations are manipulated in parallel on each partition, individually. A new method is proposed that distributes test packets and collects test responses, simultaneously. Simulation results were also compared with some prior works by means of the proposed mechanism indicating that delivering test packets’ latency was decreased about 63% and the total number of hop counts to reach the specified destination was declined approximately 34%.

Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but also the bandwidth requirements. In this paper we provide a quantitative analysis of two distinctive TDC methods from the system integrator's standpoint considering a core based SOC environment. The proposed analysis addresses four parameters: compression ratio, test application time, area overhead and power dissipation. Based on our analysis, some future research directions are given which can lead to an easier integration of TDC in the SOC design flow and to further improve the four parameters.

A new software-based hybrid test vector compression method for testing system-on-a-chip (SOC) using an embedded processor is presented in this paper. In the proposed approach, a software program is first loaded into the on-chip processor memory core together with the compressed test data set. In order to reduce on-chip storage as well as testing time, the large volume of test data input is compressed in a hybrid fashion before being downloaded into the processor. The method combines a set of adaptive coding techniques for the required test data compression. The compression program, however, need not be loaded into the embedded processor, since only the decompression of test data is necessary for application by the automatic test equipment (ATE). Most importantly, this software-based hybrid scheme requires minimal hardware overhead, while the on-chip embedded processor core can be reused for normal operation after the testing is completed. In the paper, only the compression part of the technique is presented, and the efficiency of the suggested hybrid approach is demonstrated through simulation experiments on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

SoC companies always look for ways to cut manufacturing costs. Test time reduction is one way to lower test cost. This paper proposes a new method where the test codes are loaded concurrently to various SOC memories. This parallel load reduces memory test time on ATE (Automated Test Equipment). With a few additional pins, this new control logic uses available memory bus connectivity to test internal memories concurrently at its native system speed. The proposed system is applied on large SoC having multiple DDR memory controllers or cores. The empirical analysis shows that it reduces memory controller test time substantially (~50%).

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especially for low-cost device. One of the major factors of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithms have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this example, approximate 33% of test time reduction observed for 1 Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.

Load board verification is normally performed by IC manufacturers on an automatic test equipment (ATE) as per of the standard test procedure prior to final test. Since test load boards are used as an interface between the automatic test equipment (ATE) and integrated circuit (IC), it is thus important to ensure that a particular load board is functioning otherwise the test integrity of all IC tested using the board will be questionable. As load boards become increasingly complex and difficult to verify accurately, IC manufacturers may need to use in-circuit testing as an addition to load board verification. Traditional in-circuit test platforms are expensive to implement due to cost in the bed-of-nails fixture. With the introduction of flying-probe in-circuit test platforms, this option is now a cost-viable solution. This paper discusses the issues that surround the combined test strategy of flying-probe in-circuit test and load board verification on an ATE. It goes on to propose a structure test strategy to combine both test platforms. Finally, the results and discussion are presented.

The Automatic Test System (ATS) Executive Directorate (ED) is charged with developing objectives for the Department of Defense (DoD) ATS modernization. The DoD ATS Framework Working Group (FWG) was established by the ATS ED to create a Framework addressing these objectives. The FWG consists of two sub-groups; Management, that includes members from all of the DoD Services, and Technical. The Framework is made up of key elements and associated specifications and standards that form the open system architecture approach for DoD ATSs. In addition to creating and updating key element definitions, the FWG focuses on identifying commercial ATS related specifications that might satisfy the elements in the Framework. The standards specified in the DoD ATS Framework are documented in the DoD's Information Technology Standards Repository (DISR) and thereby become a mandatory requirement for all DoD ATS acquisitions. The Framework is also being specifically called out in DoD ATS requirements documents so that its standards are incorporated in future DoD ATS acquisitions, such as the Navy's eCASS. Although the ATS Framework was originally defined more than 10 years ago, it continues to evolve as test technology evolves. A function of the FWG is to continually assess the Framework and plan the development and demonstration of specifications and standards to satisfy ATS Framework requirements. The FWG is currently participating in the standards development process via standards organizations, consortia, and working groups. The FWG is evaluating these standards in terms of applicability to the twenty plus key elements defined in the Framework. The FWG is also continually evaluating new test and information technologies to further refine and add new key elements. When necessary, the FWG provides requirements and potential solutions to standards development teams so that the resulting standard will fit within the Framework. When these standards are published and proven to meet the requirements of a particular Framework element, the FWG makes recommendations to the DoD's ATS Management Board (AMB) regarding how these standards should be represented in the DISR. Standards which are mandated will be required by the acquisition process, and vendors' products acquired by the DoD must conform to them. This paper will provide a summary of the current activities and issues impacting the ATS Framework with a discussion of the near term plans of the FWG. It will provide status on the key elements that the FWG members are currently working on. These elements include the Adapter Functional and Parametric Data (AFP), Diagnostic Data (DIAD), Diagnostic Services (DIAS), Instrument Functional and Parametric Data (IFP), Master Conformance Index (MCI), Maintenance Test Data (MTD), Resource Adapter Interface (RAI), Run Time Services (RTS), Prognostics and Health Management (PHM), and Test Station Functional and Parametric Data (TSFP). The standards that satisfy or partially satisfy these key elements, and the current status of these standards are discussed. The paper also describes the purpose of, and the FWG's role in, several industry working groups; including LAN extensions for Instrumentation (LXI), Institute of Electrical and Electronics Engineers (IEEE) Standards Coordinating Committee 20 (SCC20), Interchangeable Virtual Instruments (IVI), and Synthetic Instruments Working Group (SIWG). Finally, current issues, such as how signal modeling is to be incorporated within the Framework, the relationship to the DoD's efforts with those of the UK Ministry of Defense (MoD), the use of the DISR mandated elements in upcoming DoD ATS acquisitions, and how O-level test capabilities could be incorporated in the Framework are discussed.

Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.

The increasing test data volume is considered as a biggest challenge in circuit under test. This challenge leads to higher computational complexity associated with the testing circuits. To reduce the testing time and addresses the problem related to high overhead, high fault coverage andincreased power dissipationmethod is used in system-on-chip (SoC). A new test compression method called divide and compress (D&C) lossless compression coder with Discrete Cosine Transformis used to enhance the compression capability. This framework of D&C lossless compression coder combines the lossless and lossy compression methods. The Discrete Cosine Transform (DCT) manipulates each data bit inside file and this reduces the file size without any data loss after decoding to lossless compression.Depending on the data characteristic, the compression of data is done without any loss in data. Further, the decompression is attained using advanced Finite State Machine (FSM) to reduce overhead. The experimental results on large benchmark circuits like ITC’99 and ISCAS’99 proves that the proposed D&C lossless compression attains reduced testing time and better compression ratio. Further, itlays only soft burden on the hardware.

Higher circuit densities in System-on-a-Chip (SoC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. In order to reduce the volume of SoC test data, an improved FDR code was proposed, called Variable Prefix Dual-Run-Length Code. This coding scheme has two steps: firstly, the don't care bits in the test data are filled with 0s or 1s using the Dynamic Programming Algorithm (DPA); then according to the novel partition way, the test data was divided as alternate runs of 0's and 1's, and the 0 runs and 1 runs was encoded. Due to its simple architecture, the decompression circuit for this proposed code needs only little additional hardware. Experimental results for the ISCAS'89 benchmark circuits show that the proposed code outperforms other similar codes in achieving higher compression ratio and requiring smaller area overhead for the on-chip decoder.

In this paper, we present a new test data compression method for intellectual property (IP) cores testing, based on the reuse of parts of dictionary entries. Two approaches are investigated: the static and the dynamic. In the static approach, the content of the dictionary is constant during the testing of a core, while in the dynamic approach the testing of a core consists of several test sessions and the content of the dictionary is different during each test session. The efficiency of the proposed method is supported with extensive simulation results and comparisons to already known test data compression methods suitable for IP cores testing.