Vector based Analog to Digital Converter sequential testing methodology to minimize ATE memory and analysis requirements

An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.

The purpose of this paper is to present a conceptual approach and to make practical recommendations on how to improve the current Automatic Test Equipment (ATE) testing and maintenance capabilities by utilizing the existing cloud computing model to build a globally linked ATE maintenance system. The basic tenet of the ATE community is to support a multi-tiered maintenance concept which, in general, is a three tiered system that is composed of organizational maintenance (O-level), intermediate maintenance (I-level), and depot maintenance (D-level) organizations. The goal of the ATE is to (1) quickly and accurately detect and isolate each fault, (2) provide software tools for analyzing historical data, and (3) gather, manage, and distribute accurate and reliable maintenance information for the failed Unit Under Test (UUT). The ATE system should provide services that will (1) maintain a repository of information that will improve fault detection and isolation, allow for off-platform assessments, document failures, and help quantify corrective actions, (2) reduce false UUT pulls, and (3) reduce repair time by prompting repair procedures. Furthermore, the ATE system should provide additional services that will help optimize the time to diagnose problems by using collected failure information and by recommending entry points into the Test Program Set (TPS) software. It should also present information to the ATE maintainer to aid in informed repair decisions which could be in the form of pilot debrief results, platform Built In Test (BIT) results, O-level test outcomes and corrective actions, and maintenance and usage history of the platform and UUT. So, based on this definition of ATE maintenance the use of cloud computing can be used to provide services to improve the overall ATE testing throughput which will result in bottom line improvements to ATE life cycle costs. By using cloud computing, which is defined to be “a model for enabling ubiquitous, convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction”, users can develop cloud computing models that will provide access to application software and databases that can be used to build a globally linked ATE maintenance system. This paper will discuss the essential characteristics of the cloud computing models and define the various flavors of cloud offerings available to designers today. This paper will also analyze the cloud computing model to arrive at a conceptual approach that can be used to enhance the current ATE Testing and Maintenance capabilities. Practical recommendations will be discussed on how to transform the current ATE Testing and Maintenance capabilities into the specific cloud computing model offerings in order to help configure a globally linked ATE maintenance system.

We introduce a novel procedure for testing the dynamic parameters of analog to digital converters (ADC). The test response of the ADC is compared with a reference signal which is supplied by the tester. The evaluation of the parameters is done in time domain in real time. The method has the potential for being very advantageously implemented as a built-in self-test (BIST) into a mixed signal circuit. Goal of the development was to reduce test time significantly compared to the state of the art methods. With regard to a BIST solution another essential requirement was to keep the complexity of the test circuitry as low as possible, to get only a small additional chip area for realization. Both goals were reached successfully. The test time was reduced to a quarter and the number of gates needed is smaller than 6,700. In a first step the algorithm was modeled at system level and the correctness of the procedure was proven by simulations. To get a reliable estimation of the number of gates necessary for an implementation, the optimized model was redesigned in VHDL. Based on the VHDL code a field programmable gate array (FPGA) was configured which led to the gate count estimation. Measurements on a Teradyne J750 tester showed that the accuracy of the method is equivalent to FFT based methods.

Testing high-speed analogue and mixed-signal designs, in particular, is becoming a more difficult task, and observing critical nodes in a system is becoming increasingly challenging. As the technology keeps scaling, especially past the 90 nm technology, metal layers and packing densities are increasing as a function of signal bandwidth and rise times extending beyond the gigahertz range. Automatic test equipment (ATE) interface has become a major bottleneck to deliver signals with high fidelity, due to the significant distances the signals have to travel at such operational speeds. Test solutions can be placed on the chip and are then known as a structural test or built-in self test (BIST), on the board level or as part of the requirements of the ATE.

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 ?m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

One of the important steps that a semiconductor chip goes through is electrical testing, which typically is performed on an automated test equipment (ATE) platform. The primary goal of this step is to achieve maximum test coverage while minimizing testing time as much as optimal. There are various test methods used in testing, ranging from a simple continuity test to implementations such as built-in self-tests (BISTs) in which the chip is instructed to run internally and the test program checks for the result only when it is done. BISTs are, in a way, non-deterministic in nature; testing time can vary depending on the internal clock frequency at which the test is run and other factors based on the chip's operation. One way to optimize testing time of non-deterministic tests at ATE is to read the results register immediately on completion of the BIST execution, and not wait for a hard-coded amount of time to elapse - typically, an amount of time based on the slowest possible test execution to complete. This paper discusses a method that eliminates unnecessary time lost waiting for data that may have long arrived.

There is a tremendous demand for analog to digital converters in the continuously increasing digital world. They are the most significant mixed-signal blocks acting as the interface between the analog and the digital world. Integrating these analog circuits into digital systems is challenging as the digital circuits limit the speed and accuracy of the converters. A wide range of analog to digital converters is available. The pipeline analog to digital converters provide high throughput from few mega-samples per second to greater than 100 mega-samples/second and resolution ranging from eight to sixteen bits. This paper deals with behavioral and CMOS level modeling of 10-bit pipeline ADC. It has been observed that fully circuit level simulations take a lot of time. Hence, co-simulation is a better alternative. Here, co-simulation has been performed among the behavioral and circuit modules and their corresponding outputs have been compared. Finally, the throughput and INL/DNL has been calculated. Keywords—Pipeline ADC, throughput, mixed-signal, resolution, behavioral, CMOS.

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especially for low-cost device. One of the major factors of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithms have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this example, approximate 33% of test time reduction observed for 1 Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.

By embedding an expert system into portable automatic test equipment (ATE) the sophistication and capability of the testing system was increased while maintaining the compactness of the portable ATE. The results of this effort are presented, and include reductions in both the number and size of fault ambiguity sets, and the ability of the system to detect and isolate multiple faults. By combining information from built-in-test (BIT) results, user observations, and failure histories, the mean time to repair was reduced because utilization of this information permitted dynamic creation of an optimal test sequence. In addition, the recommendations presented have a greater amount of confidence associated with them because the intelligent maintenance aid (IMA) allows enhancement of existing ATE without major modifications to the hardware. >

As more and more peripherals are integrated in System-On-Chip (SoC), the production testing cost per device is increasing sharply, which is eating up the gross margin of the product significantly. This paper proposes an alternate scheme for production testing whereby major part of the SoC testing can be done with a pre-tested and pre-verified custom made SoC. It will help to minimize the dependencies of Automatic Test Equipment (ATE) for SoC testing in production significantly. Hence production testing cost per device will be reduced. Also this scheme will enable to test many of the functional features of SoC on silicon, which were not possible to test using ATE due to high test cost. In this paper the micro architectural details of the scheme, system requirements, design challenges and case study conducted on different SoCs are presented. And the impact of this approach is also discussed.

The low throughput at IC (integrated circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (automatic test equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (multiple-input signature register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).

This research project aims to expand the capability of current US Navy Automated Test Equipment (ATE) family of testers known as the Consolidated Automated Support System (CASS). Industry research is now focused on breaking the historical construct of test equipment. Advances in the field of Synthetic Instruments have opened the door to test avionics in new ways. Every year new capabilities are developed using core hardware and increasingly capable software modules to create complex waveforms. This research creates a Digital Radio Frequency Memory (DRFM) Synthetic Instrument that can be programmed to perform a wide array of low latency Radio Frequency (RF) tests. Synthetic Instruments are defined as a concatenation of hardware and software modules used in combination to emulate a traditional piece of electronic instrumentation. This Synthetic Instrument couples high speed Analog-to-Digital Converters (ADC) to high speed Digital-to-Analog Converters (DAC) with Field Programmable Gate Arrays (FPGA) in between for digital signal processing. An RF front end is used to down convert the RF to baseband where it is sampled, modified, and up converted back to RF. The FPGA performs Digital Signal Processing (DSP) on the signal to achieve the desired output. Application of this DRFM in automated testing is demonstrated using a Reconfigurable Transportable Consolidated Automated Support System (RTCASS) tester at Naval Air Systems Command (NAVAIR) Jacksonville, FL. The Unit Under Test (UUT) is an ALQ-162 Defensive Electronic Countermeasures (DECM) receiver-transmitter. Ultra-low latency signals are generated to simulate enemy jamming stimulus. As the ALQ-162 detects and responds to the input, the DRFM switches to a new frequency. The time taken by the ALQ-162 to acquire, respond, and re-acquire is measured. This test confirms the internal Yttrium Iron Garnet (YIG) oscillator meets slew specifications. Currently Navy ATE can only test RF units using high latency steady state tests. This research project developed a supplemental unit that can be added to the VXI chassis in the CASS family of testers and conduct ultra-low latency active tests. The instrument acts as hardware-in-the-loop to perform real-time tests including a new capability to measure jamming response time from DECM avionics. Demonstrated performance capabilities include: latency <; 100 ns, output Spurious-Free Dynamic Range (SFDR) > 80 dBc, input SFDR > 60 dBc, frequency tuning resolution <; 2 Hz, and frequency settling time <; 0.5 ns. New RF capabilities developed by this effort parallel similar research ongoing for digital test instruments like the Teradyne High Speed Subsystem. Incorporating this Digital RF Memory synthetic instrument into current and future ATE will improve readiness and supportability of the fleet. Improvements demonstrated by this research project will expand the type and quantity of assets able to be tested by current and future ATE.

This paper describes how using a phase switching technique can produce a low distortion signal from an Arbitrary Waveform Generator (AWG), and how this technique aligns the performance of the AWGs between testers, to evaluate the Total Harmonic Distortion (THD) performance of Analogue-to-Digital Converters (ADCs). Once a device has been characterized and correlated to the bench, the test engineer needs to start the release procedure in getting the device into a production ready state. One major issue that a test engineer faces is the difference in ADC THD performance test results using the same Automated Test Equipment (ATE) manufacture testers (AWGs). This paper will then show how the Gauge Repeatability and Reproducibility (GRR) between testers can be produced more easily allowing less stringent guard-bands to guarantee the performance of those devices that have performance criteria close to the device specification. This work will also go some way to proving previous papers' works on distortion shaping testing to enhance the spectral performance of Arbitrary Waveform Generators.