An Architecture for Combined Test Data Compression and Abort-on-Fail Test

Integrated circuit (IC) applications have become viable, reliable, and cheaper with deep-submicron technologies in VLSI industry. SoC (system on chip) is a microchip, which holds the necessary hardware and software to implement various functions onto a single chip. An IC should be tested during design process to check the correctness of the design and also to check the functionality of the design after fabrication. Testing cost shares almost half of the manufacturing expenditure. Achieving high-test quality in reduced VLSI geometry increases the complexity of the testing methods because of huge volume of test data. Automatic testing equipment (ATE) reduces testing efforts, but it has limited memory in comparison with the huge volume of the test data. One of the methods to reduce the burden of ATE is test data compression. The advantages of test data compression are as follows: (i) reduction in memory requirement for ATE and (ii) reduction in testing time. Though many advanced algorithms are used for testing of VLSI circuits, most of them are expensive in terms of test data volume and power. This survey discusses all the test data compression methods, and it helps the researchers in testing domain.

Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the proposed scheme gives the better test data compression compared to very recently proposed encoding schemes for any test set. It is clearly demonstrated with a large number of experimental results that the proposed scheme improves the test data compression, reduces overall test application time and on-chip area overhead compared to other Huffman code based schemes.

Green energy sources such as solar power, wind, and biomass ... are getting more attention especially after the nuclear crisis caused by earthquake in Mar. 2011 in Japan. The solar power has been considered to be the major contributor of the green energy. There are more than enough solar irradiations available to satisfy the world's energy demands. However the traditional photovoltaic (PV) systems suffer from various power losses, the performance shows average losses of about 20%-30% in electricity production. Some companies provide advance system architectures which can boost solar panel output power by up to 20%-25%. One of a key element of the system is the DC-DC converter [1]. Texas Instruments' high voltage gate driver ICs (HVIC) can be used as a DC-DC converter, half/full bridge applications or class-D audio amplifiers. There are challenges for the HVIC testing. First, the timing measurements for propagation delay matching in both buck and boost which need to be in nanoseconds range but the typical production automatic test equipment (ATE) specification of timing measurement unit (TMU) accuracy is approximate 2 nanoseconds (ns) and meanwhile, the output voltage of gate driver application can exceed 100 volts. Second, test time and multi-site testing have to be considered. In this paper, we have discussed the critical timing measurements and have successfully implemented the multi-site delay matching testing on IFLEXTM ATE platform with 100 picoseconds (ps) resolution while the boost is operating at 120V.

Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but also the bandwidth requirements. In this paper we provide a quantitative analysis of two distinctive TDC methods from the system integrator's standpoint considering a core based SOC environment. The proposed analysis addresses four parameters: compression ratio, test application time, area overhead and power dissipation. Based on our analysis, some future research directions are given which can lead to an easier integration of TDC in the SOC design flow and to further improve the four parameters.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

Test data volume amount is increased multi-fold due to the need of quality assurance of various parts of the circuit design at deep submicron level. Huge memory is required to store this enormous test data which not only increases the cost of the ATE but also the test application time. This paper presents an optimal selective count compatible run length (OSCCPRL) encoding scheme for achieving maximum compression for reduction of the test cost. OSCCPRL is a hybrid technique that amalgamates the benefits of other two techniques: 10 Coded run length (10 C) and Selective CCPRL (SCCPRL) proposed here. These techniques work on improvement of the 9 C and CCPRL techniques. In OSCCPRL, entire data is segmented in blocks and further compressed using inter block and intra block level merging techniques. SCCPRL technique is used for encoding the compatible blocks while the 10C is used to do encoding at sub block (half block length) level. In case, if no compatibility is found at block/sub block level then the unique pattern is held as such in the encoded data along with the necessary categorization bits. The decompression architecture is described and it is shown how by just the addition of few states of FSM, better test data compression can be achieved as compared to previous schemes. The simulation results performed for various ISCAS benchmarks circuits prove that the proposed OSCCPRL technique provides an average compression efficiency of around 80 %.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a a major challenge to test 2.5 ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this work, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. Compared to previous work, the proposed technique can reduce testapplication time by 53:4% for benchmark designs while achieving higher fault coverage.

As the design complexity increases, three-dimensional (3D) integrated circuit (IC) design has become an industry trend. However, the testing of a 3D IC is a design challenge. In addition to minimize the test application time (including pre-bond testing and post-bond testing), the number of test pads of each layer should also be taken into account. In this paper, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling with test pads considered. Different from those previous works, our objective is to minimize the weighted sum of the test application time and the number of required test pads. Experimental results consistently show that our approach works well in practice.

Three issues that are dominating test research today are test application time, test data volume and test power. Researchers have focused on these issues mostly considering the popular serial scan architecture for its relatively low hardware overhead while ignoring the fact that exponential drop in hardware cost offers opportunities for implementing a test architecture that previously may have been unacceptable. This paper takes such a paradigm shift into account and studies the simultaneous solution of all three problems of serial scan by making use of progressive random access scan test architecture. This architecture only increases the hardware cost marginally while providing marked improvements for the three issues. This paper explains the test architecture and then develops a test generation methodology which reduces the test application time by nearly 75%, test data volume by 50% for the benchmark circuits. Above all, the architecture is inherently so efficient that it reduces the test power by nearly 99% or more of the test power consumption compared to serial scan

This paper presents a comprehensive hybrid test vector compression method for very large scale integration (VLSI) circuit testing, targeting specifically embedded cores-based system-on-chips (SoCs). In the proposed approach, a software program is loaded into the on-chip processor memory along with the compressed test data sets. To minimize on-chip storage besides testing time, the test data volume is first reduced by compaction in a hybrid manner before downloading into the processor. The method uses a set of adaptive coding techniques for realizing lossless compression. The compaction program need not to be loaded into the embedded processor, as only the decompression of test data is required for the automatic test equipment (ATE). The developed scheme necessitates minimal hardware overhead, while the on-chip embedded processor can be reused for normal operation on completion of testing. This paper reports results on studies of the problem and demonstrates the feasibility of the suggested methodology with simulation runs on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits.

The objective involves in construction of a Logical Built in Self Test using adaptive Multiple Input Signature Register designs that is mainly used for testing of the Integrated Circuits. One of the major issues is that, the complications in integrated circuit testing have been increased due to the emerging trends in the field of Very Large Scale Integration. This problem could be solved by increasing the usage of test equipment named Logical Built in Self Test shortly called as LBIST which works much well than any other test equipments. The logical BIST also has the advantage of performing a test that is in-built to the chip by means of an extra element that is present interior to the design. Test patterns for the operation are generated always by an inbuilt testing circuit as mentioned earlier. The output responses are determined with the help of a Multiple Input Signature Register, which is the most widely as the design is completely opposite to that of a Linear Feedback Shift Register design. The testing methodology is always invoked by a MISR by means of compressing multiple sequences of input bits as a single package named as signature of the design. The fault performance during a chip testing can be improved by means of a reconstructable Linear Feedback Shift Register which functions both to generate test patterns as well as to compress the responses required for logical Built in Self Testing. The QUCS simulator and SPICE tool is used to perform compilation of fast Multiple Input Signature Register design. Four structural representations namely Basic, Combined, Programmable and Advanced MISR are implemented and simulated using QUCS simulator and SPICE tool in 22nm technology. The output waveforms of the adaptive designs are obtained for different temperature variations ranging from 27°C to 107°C.

Load board verification is normally performed by IC manufacturers on an automatic test equipment (ATE) as per of the standard test procedure prior to final test. Since test load boards are used as an interface between the automatic test equipment (ATE) and integrated circuit (IC), it is thus important to ensure that a particular load board is functioning otherwise the test integrity of all IC tested using the board will be questionable. As load boards become increasingly complex and difficult to verify accurately, IC manufacturers may need to use in-circuit testing as an addition to load board verification. Traditional in-circuit test platforms are expensive to implement due to cost in the bed-of-nails fixture. With the introduction of flying-probe in-circuit test platforms, this option is now a cost-viable solution. This paper discusses the issues that surround the combined test strategy of flying-probe in-circuit test and load board verification on an ATE. It goes on to propose a structure test strategy to combine both test platforms. Finally, the results and discussion are presented.

The Automatic Test System (ATS) Executive Directorate (ED) is charged with developing objectives for the Department of Defense (DoD) ATS modernization. The DoD ATS Framework Working Group (FWG) was established by the ATS ED to create a Framework addressing these objectives. The FWG consists of two sub-groups; Management, that includes members from all of the DoD Services, and Technical. The Framework is made up of key elements and associated specifications and standards that form the open system architecture approach for DoD ATSs. In addition to creating and updating key element definitions, the FWG focuses on identifying commercial ATS related specifications that might satisfy the elements in the Framework. The standards specified in the DoD ATS Framework are documented in the DoD's Information Technology Standards Repository (DISR) and thereby become a mandatory requirement for all DoD ATS acquisitions. The Framework is also being specifically called out in DoD ATS requirements documents so that its standards are incorporated in future DoD ATS acquisitions, such as the Navy's eCASS. Although the ATS Framework was originally defined more than 10 years ago, it continues to evolve as test technology evolves. A function of the FWG is to continually assess the Framework and plan the development and demonstration of specifications and standards to satisfy ATS Framework requirements. The FWG is currently participating in the standards development process via standards organizations, consortia, and working groups. The FWG is evaluating these standards in terms of applicability to the twenty plus key elements defined in the Framework. The FWG is also continually evaluating new test and information technologies to further refine and add new key elements. When necessary, the FWG provides requirements and potential solutions to standards development teams so that the resulting standard will fit within the Framework. When these standards are published and proven to meet the requirements of a particular Framework element, the FWG makes recommendations to the DoD's ATS Management Board (AMB) regarding how these standards should be represented in the DISR. Standards which are mandated will be required by the acquisition process, and vendors' products acquired by the DoD must conform to them. This paper will provide a summary of the current activities and issues impacting the ATS Framework with a discussion of the near term plans of the FWG. It will provide status on the key elements that the FWG members are currently working on. These elements include the Adapter Functional and Parametric Data (AFP), Diagnostic Data (DIAD), Diagnostic Services (DIAS), Instrument Functional and Parametric Data (IFP), Master Conformance Index (MCI), Maintenance Test Data (MTD), Resource Adapter Interface (RAI), Run Time Services (RTS), Prognostics and Health Management (PHM), and Test Station Functional and Parametric Data (TSFP). The standards that satisfy or partially satisfy these key elements, and the current status of these standards are discussed. The paper also describes the purpose of, and the FWG's role in, several industry working groups; including LAN extensions for Instrumentation (LXI), Institute of Electrical and Electronics Engineers (IEEE) Standards Coordinating Committee 20 (SCC20), Interchangeable Virtual Instruments (IVI), and Synthetic Instruments Working Group (SIWG). Finally, current issues, such as how signal modeling is to be incorporated within the Framework, the relationship to the DoD's efforts with those of the UK Ministry of Defense (MoD), the use of the DISR mandated elements in upcoming DoD ATS acquisitions, and how O-level test capabilities could be incorporated in the Framework are discussed.