3D IC test scheduling with test pads considered

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC’99 b19 benchmark is only about 0.15%.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a a major challenge to test 2.5 ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this work, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. Compared to previous work, the proposed technique can reduce testapplication time by 53:4% for benchmark designs while achieving higher fault coverage.

With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.

We describe a design problem arising in the color printing industry and discuss a number of integer linear programming and constraint programming approaches to its solution. Despite the apparent simplicity of the problem it presents a challenge for both approaches. We present results for three typical cases and show that the constraint programming approach provides better results, although in some cases after considerable handcrafting. We also show that the results obtained by constraint programming can be improved by a simple goal programming model.

Core based three-dimensional(3D) integrated circuits (ICs) design is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced power consumption. But due to scaling in technology features these chips are more complex and hence testing of these 3D ICs is a challenging task. This paper follows a P1500-style wrapper design for 3D ICs using through silicon vias (TSVs) for testing purpose. It is assumed that the core elements are distributed over several layers of the ICs. As the number of available TSVs are limited due to small chip area, this work is intended to design balanced wrapper chains using available TSVs. In this work we have proposed a polynomial time algorithm of O(N) to design the test wrapper. The results are presented based on the ITC'02 SOC test benchmarks and compared with prior work. Obtained results show that our algorithm provides better utilization of TSVs compared to the work presented in.

Scheduling educational institution courses for multiple departments presents a significant challenge due to the complexity of constraints and requirements. This paper addresses the University Course Scheduling Problem (UCSP) using a binary Integer Linear Programming (ILP) approach to generate semester schedules for winter or summer semesters. The approach incorporates both hard constraints - such as avoiding simultaneous sessions for the same semester, adhering to room capacities, and ensuring lecturers are not doublebooked - and soft constraints, including preferences for lecture times. While the whole methodology integrates tools for data management, optimization modeling, and a structured workflow to create detailed schedules for lecturers, students, and room allocations, this paper focuses on the ILP-formulation of these constraints. The construction of these matrices is systematically explained through practical examples, illustrating how the relationships between courses, lecturers, rooms, and time slots are encoded. To validate the proposed approach, a case study was conducted at the Niederrhein University of Applied Sciences. This study addresses the scheduling requirements of three engineering departments with more than 50 degree programs and 260 modules, demonstrating the applicability of the matrixdriven ILP method.

With the advent of deep sub-micron era, there is a demand to consider the design closure problem in high-level synthesis. It is well known that the slack is an effective means of tolerating the uncertainties in operation delays. Previous work ever attempted to increase the usable slack based on a given initial schedule. Instead of the post-processing approach, this paper is the first attempt to the simultaneous application of operation scheduling and slack optimization. We use a 0-1 integer linear programming (0-1 ILP) approach to formally formulate the problem. Under the design constraints (timing and resource), our approach is applicable to two different objective functions: the maximization of the total usable slack and the maximization of the number of non-zero slack operations. Compared with previous work, our approach has the following two advantages: first, our approach guarantees the optimality; second, our approach is more suitable for the design space exploration.

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

Because of the reduction of wire length, three-dimensional integrated circuit (3D IC) technology can improve the circuit speed and reduce the power dissipation. However, the heat generated by the stacked layers may result in a very large amount of temperature rise. Therefore, in the design of three-dimensional integrated circuit, it is very important to reduce the temperature rise. Although previous works have addressed the relation between layer assignment and temperature rise, they do not consider the utilization of thermal through-silicon-vias (TSVs). Based on that observation, in this paper, we are motivated to perform simultaneous layer assignment and thermal TSV planning for further temperature rise reduction. We propose an integer linear programming approach to solve this problem optimally. Compared with previous works, experimental results show that our ILP approach can achieve a large amount of temperature rise reduction.

This chapter presents a linear-programming-based optimal solution for an Optimal Placement Problem (OPP) of Synchrophasors or Phasor Measurement Units (PMU). With the increasing use of Synchrophasors for smart-grid monitoring and control, the problem with PMU placement has become a major concern due to its large installation costs. This chapter utilizes an Integer Linear Programming (ILP) approach to find optimal solutions. We show that the performance of our LP constraints and the formulation makes the ILP approach very attractive for smaller utilities that have limited budgets. This is shown using with and without zero-injection cases in programmed AMPL language using CPLEX solver. We also propose an Optimal Redundancy Criterion (ORC) which assists utilities with providing redundant observability for critical buses in the system. Our approach yields full and redundant observabilities within a few milliseconds for different cases, such as IEEE 300 test systems and an Indian power grid.

Purpose This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs). Design/methodology/approach This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package. Findings This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package. Research limitations/implications Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed. Practical implications The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board. Social implications In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model. Originality/value The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

The low throughput at IC (integrated circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (automatic test equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (multiple-input signature register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).

The semiconductor industry has been regarded as one of the most important industries by Taiwan due to the market share of Taiwan’s semiconductor industry in 2011 ranked second worldwide. However, the European debt crisis triggered a global economic recession in 2011, causing Taiwan’s output of semiconductors in 2010 and 2011 to show negative growth. This paper will mainly explore, from the performance evaluation perspective, the Malmquist productivity index of the Taiwan’s semiconductor industry based on a metafrontier approach. The empirical results show that the European debt crisis in 2011 had an impact on Integrated circuit (IC) design companies and IC manufacturing companies, but that there was no influence on IC packaging and testing companies when measuring static efficiency. From the viewpoint of dynamic productivity performance, the paper finds that the main reason for the negative growth of IC packaging and testing companies and IC design companies came from a backward movement in technical change, but the main reason for the negative growth of IC manufacturing companies derived from a decline in pure technical efficiency.

PurposeTo determine the status of internet and e‐commerce adoption by the Taiwan semiconductor industry, the research is designed to help government and enterprise in formulating strategic plans and making resource allocation decisions.Design/methodology/approachUsing the three‐level model of internet commerce adoption (MICA), a survey of 287 companies and web sites was designed. Semiconductor firms were placed into five categories: integrated circuit (IC) design, manufacturing, packaging, IC testing, and peripheral device manufacturing.FindingsThe MICA model shows the internet adoption ratio for semiconductor firms as 82.6 percent, significantly higher than the electronics and electrical machinery industry sector (56.5 percent). The IC manufacturing and packaging segment are in the processing stage, the final stage of development for the MICA model. One‐third of the IC testing industry segment falls into the provision stage, and 36.1 percent web sites are in the processing stage. The IC design and peripherals industrial segments are located in the provision stage.Practical implicationsThe IC manufacturing segment is conducting more financial transactions than the other segments – a result that matches earlier research showing that larger companies are most likely to implement e‐business applications. Many enterprises in the industry are lagging with the adoption of the internet indicating a need for education and training.Originality/valueThis benchmark study provides a framework for evaluating the internet adoption status of semiconductor and other high technology firms. The MICA model is demonstrated to be suitable for evaluating the different stages of internet adoption.