PERFORMANCE EVALUATION OF THE SEMICONDUCTOR INDUSTRY BASED ON A METAFRONTIER APPROACH

In semiconductor manufacturing, time-to-market is critical to maintain a competitive advantage through achieving customer satisfaction. Inefficient ways of utilising production resources will lead to a long cycle time. Therefore, machine allocation becomes an essential production decision in many practical manufacturing systems, especially for integrated circuit (IC) packaging. IC packaging is the process of encasing the finished die in a package in order to prevent corrosion and physical damage. Advanced IC packaging techniques add even more complexity into the production system, so reliable average cycle time of this complex system becomes difficult to obtain. We propose a new simulation optimisation framework with multi-fidelity models to study an IC packaging case of the machine allocation problem to pursue a minimum average cycle time. This framework consists of two methodologies: ordinal transformation (OT) and optimal sampling (OS). The OT first employs the low-fidelity model to fast observe all designs, and extracts insightful information from this model by transforming the original design space into an ordinal space. It follows that OS efficiently allocates the computing budget for searching the best design via high-fidelity simulations. An empirical study based on real data was conducted to validate the practical viability of the proposed framework.

PurposeTo determine the status of internet and e‐commerce adoption by the Taiwan semiconductor industry, the research is designed to help government and enterprise in formulating strategic plans and making resource allocation decisions.Design/methodology/approachUsing the three‐level model of internet commerce adoption (MICA), a survey of 287 companies and web sites was designed. Semiconductor firms were placed into five categories: integrated circuit (IC) design, manufacturing, packaging, IC testing, and peripheral device manufacturing.FindingsThe MICA model shows the internet adoption ratio for semiconductor firms as 82.6 percent, significantly higher than the electronics and electrical machinery industry sector (56.5 percent). The IC manufacturing and packaging segment are in the processing stage, the final stage of development for the MICA model. One‐third of the IC testing industry segment falls into the provision stage, and 36.1 percent web sites are in the processing stage. The IC design and peripherals industrial segments are located in the provision stage.Practical implicationsThe IC manufacturing segment is conducting more financial transactions than the other segments – a result that matches earlier research showing that larger companies are most likely to implement e‐business applications. Many enterprises in the industry are lagging with the adoption of the internet indicating a need for education and training.Originality/valueThis benchmark study provides a framework for evaluating the internet adoption status of semiconductor and other high technology firms. The MICA model is demonstrated to be suitable for evaluating the different stages of internet adoption.

The need for compact models of Integrated circuits (IC) is a well-recognized problem in electronics cooling simulations of electronic systems. Simplified thermal models have been reported in the literature to simulate the transient thermal behavior of IC devices. Most of the simplification approaches require a pre-determined topology of a resistance-capacitance (RC) network. Multigrid technique allows for automatically constructing both the topology and characteristics of the reduced-order or compact models of devices (primarily IC packages) for use in system-level simulations. In this study, we report an approach where the topology and the nodal RC values of the network are automatically generated. The procedure is also applicable for complex IC sub-systems or systems like multi-chip modules, stacked die package, system-in-package, and CPU module, and hard drives. In the study report herein, the method is applied to three types of IC packages. The first package is a 196-pin fine pitch ball grid array (FBGA15/spl times/15/spl I.bar/196 L) package. The second package is a 480-pin plastic ball grid array (PBGA+HS37.5/spl times/37.5/spl I.bar/480 L/spl I.bar/extHS) package with drop-in heat spreader. An external heat sink is attached to the top surface of the package. The third package is an 8-pin small outline IC (SOIC/spl I.bar/480 L) package with a total power dissipation of 0.5 W. RC networks are created for these packages and then used in CFD simulations for different boundary conditions, corresponding to single phase natural and forced convective cooling. The simulation results are compared to the corresponding detailed package simulations.

Efficiency and accuracy are the two main factors to develop the competence for the integrated-circuit (IC) packaging industry. An IC packaging house needs to deal with problems integrating production flows of wafer in, packaging, test, and shipping in order to provide clients instant and accurate products and services information. Radio frequency identification (RFID) technology is an effective electronic information carrying device to collect and alter data. In this study, RFID technology, combined with RosettaNet network and enterprise resource planning (ERP) system, is applied to resolve the wafer receiving and inventory transaction problems. An electronic material flow control system for IC packaging houses is developed using Oracle application implementation methodology to integrate RFID technology, RosettaNet network, and ERP system. The developed electronic material flow control system is implemented in a local IC packaging company. Results from this study suggest that labor cost and man-made errors are reduced due to the significant improvement for wafer receiving process and inventory transaction process using RFID technology. Besides that, the developed material flow control system enhances the capability of the ERP systems so as to greatly reduce operators' workload and operation costs for IC packaging houses.

In the modern business environment, process technology evaluation and selection (PTES) is a crucial component of innovation in new product development (NPD). The most difficult task for project managers in PTES is to make the optimal technology choice for a Research and Development (R&D) project, and there are many attendant uncertainties and risks in process technology R&D projects for NPD. Recently, Integrated Circuit (IC) Packaging has become an equal part of the cost-performance equation in the silicon world, and packaging foundries have responded quicker than many other semiconductor companies to the rapidly changing requirements of chip-scale packaging. This facilitates the transfer of new technology from the assemblers to the chip suppliers. This study applies the fuzzy analytic network process (FANP) model to evaluate the strategic impact of new IC manufacturing technologies in firms within Taiwan’s IC packaging industry. Our study will determine the key decision-making factors affecting R&D project selection using FANP, and additionally we develop an optimal manufacturing process. As a case study, the ongoing “Controller IC packaging R&D project A” was chosen to minimize warpage of controller IC.

Research background: Risk-taking is the basis for sustainable development of enterprise. It was clear that the influence COVID-19 epidemic on the global market economy has increased operational risks for businesses. The semiconductor industry has high operating risks and financial risks. Moderate financial flexibility (FF) can improve the ability of semiconductor enterprises to acquire financial resources in real time, calmly cope with the impact of uncertainties in operation, improve investment opportunities, and enhance sustainable operation. It is therefore interesting to study the influence of FF on enterprise risk-taking (ERT).
 Purpose of the article: The aim of the contribution is to explore the effect of FF on ERT within Taiwan?s semiconductor industry amid the COVID-19 pandemic period, and investigate whether ERT varies with semiconductor industry characteristic.
 Methods: Data from first three quarters of 2020, from multinational semiconductor firms listed on the Taiwan Stock Exchange (TSE), were collected and analyzed. Fixed effects regression with heteroscedasticity adjustment used to evaluate the influence of FF on the ERT of Taiwan?s semiconductor industry. Furthermore, in order to corroborate and support the reliability of the results, this research also used the different measures of ERT and Quantile regression (median regression) in the research model to check the robustness.
 Findings & value added: Empirical results indicate that FF has a U-shaped effect on ERT for multinational semiconductor firms listed on the TSE, particularly within the integrated circuits (IC) manufacturing industry. Additionally, FF also has a U-shaped effect on ERT for the asset-light semiconductor and IC manufacturing industries. This article also suggests that for the asset-light semiconductor and IC manufacturing industries, the optimal inflection points are 1.1397 and 0.9729, respectively. Based on the consequences of this study, it is suggested that Taiwan?s semiconductor industry should reasonably maintain FF and focus on the liquidity risk management for the long term value added, even after the COVID-19 pandemic period.

A failure criterion for debonding initiation between molding compounds and copper leadframes in plastic encapsulated integrated circuit (IC) packages is proposed. The leadframe pull-out test is used to evaluate the bond strengths between molding compounds and leadframes in plastic encapsulated IC packages. The normal and shear stress fields along the interface are analyzed using the finite element method. An average stress approach is employed for the interface failure criterion and the tensile and shear interface bond strengths are obtained from the experimental failure loads. In a parametric study, the effects of specimen loading geometry, moisture, and surface contamination of copper leadframes on the interfacial bond strengths are specifically analyzed. The results show that the interface bond strengths determined for the two specimen geometries are consistent.

In the integrated circuit (IC) packaging process, including operations of die sawing, die bonding, wire bonding, molding, plating, marking, trim/form, and inspection. Purposes of packaging include protecting ICs, making ICs easier to handle, and connecting ICs to the circuit outside. The wire bond stations are the bottleneck in the packaging and assemble process where the heat block is the key auxiliary parts in the stations. This research proposes a RFID-enabled Heat Block Management System (RHMS) to accurately control the progress of the IC packaging production line to meet the customer requirements. Our research analyzed all the flows of heat block management operations during before and after introducing RHMS. Hypothesis testing can verify significant difference between two sample sizes. Based on the statistics test of hypothesis, we compared the difference for before and after introducing RHMS. The results show that the RHMS can bring advantage for heat block management in wire bond stations. Moreover, it has clear improvement of saving counting and revising operation time. The contributions of this research are not only a case study but also a direction for applying RFID technology on IC packaging industry.

Evaluating the dynamic performances of business groups from the carry-over perspective: A case study of Taiwan׳s semiconductor industry

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

The rapidly growing incidences of counterfeit integrated circuits (ICs) pose a significant threat to the semiconductor industry. These ICs may suffer from functional, performance, or reliability issues and can affect chip manufacturers, system designers as well as end users. The standard chip/package level structural and functional tests are often inadequate in detecting various forms of counterfeit ICs. Moreover, existing design for security approaches are usually not attractive due to additional design modifications, hardware overhead, test cost, and inadequate robustness. In this paper, we propose a novel, low-overhead package-level IC integrity validation approach, referred to as P-Val, for unified protection against two primary forms of counterfeiting attacks: 1) recycling and 2) cloning. Protection against recycled/remarked chips is achieved through a unique active defense that inserts antifuses (AFs) (one-time programmable) to few select pins inside the package. It effectively disables the functionality or “locks” these pins, which need to be programmed before first-time use to make a chip functional in a system. To protect against cloned ICs, intrinsic random variations in programmed resistances of AFs connected to some of the remaining IC pins are exploited to create unique chip-specific signatures for authentication. P-Val requires no die-level design modifications and remains effective for legacy designs. Moreover, we show that it is effective for small chips with just few pins including analog ICs, where common authentication approaches fail to work. We discuss optimal choice of AF structure and program parameters; their integration in IC packages; and the signature generation/verification process. Through mathematical analysis and simulation results, we demonstrate that the proposed mechanism provides high level of protection against counterfeiting attacks at ultralow overhead (<0.05% package area).

Technical Change and Productivity Growth in the Indian Sugar Industry

This article discusses configurations of light-emitting diode (LED) light sources for visual inspection of integrated circuit (IC) packages. A package visual inspection (PVI) system with multiple LED light sources used for inspection of IC packages was designed. The image contrast changes of the sample IC packages are explained using the Torrance-Sparrow (TS) model. A few conclusions on appropriate lighting configurations for inspection of various IC packages are achieved. The TS model can be used to represent the specular lobe component. The contrast between two surfaces with different surface roughness values increases with increasing θ i (incident light angle). Lighting C (θ i = 75°) is recommended for packages with high surface roughness heights and resin materials. Lighting B (θ i = 60°) is recommended for packages with moderate surface roughness heights and metal materials. If the background is white, the use of light sources A (θ i = 15°) and B simultaneously is recommended. Light sources A and C are recommended to be chosen for packages with low surface roughness values and transparent materials. The experimental results with the actual gray-level values of the images are compared to support the conclusions. The PVI system is part of an inspection machine. All images of the sample IC packages reported in this article were obtained from an actual production line. Therefore, the results are close to those of the actual inspection situation in the manufacturing industry.

The integrated circuit (IC) industry in Taiwan is comprised mainly of IC chip design and fabrication, IC packaging, and system product design and fabrication industries. Fueled by rapid investment and development efforts from government and private sectors, this industry has sustained a rapid growth in recent years becoming one of the most profitable industries among Asian Pacific countries. This paper details Taiwan's IC packaging manufacturing capabilities and its technology trends. It describes the Taiwan IC package industry's ability to maintain favorable competitive leverage in the global business environment. This paper concentrates on two key areas of manufacturing and technology trends to illustrate Taiwan's electronic industry in general: chip-level packages and substrate and its assembly. The requirements for different applications in the future packages are discussed. The reason for the packaging paradigm shifts and associated precautions are also explained.

The author addresses the question of knowledge transfer between industry and academy in the area of integrated-circuit (IC) testing. He first examines the movement of theory from academia to industrial practice, finding two problems: designers are evaluated on meeting deadlines not on testability; and most designers do not know how to ensure testability in a systematic fashion. The solutions are technological-implementation of either design rules and design-rule checkers to guarantee testability or the use of testability measure programs-and educational, i.e. teaching design for testability as an integral part of logic design. The author then discusses the problems of teaching the relevance of theory to current industrial practice at the University ball. He finds more problems and lists the causes of the irrelevance of theory, including industry-university consulting policies, funding mechanisms that depend on peer review, and the frequent difficulty of determining the relevance of novel theory before its industrial applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>