Application of multi-fidelity simulation modelling to integrated circuit packaging

In the modern business environment, process technology evaluation and selection (PTES) is a crucial component of innovation in new product development (NPD). The most difficult task for project managers in PTES is to make the optimal technology choice for a Research and Development (R&D) project, and there are many attendant uncertainties and risks in process technology R&D projects for NPD. Recently, Integrated Circuit (IC) Packaging has become an equal part of the cost-performance equation in the silicon world, and packaging foundries have responded quicker than many other semiconductor companies to the rapidly changing requirements of chip-scale packaging. This facilitates the transfer of new technology from the assemblers to the chip suppliers. This study applies the fuzzy analytic network process (FANP) model to evaluate the strategic impact of new IC manufacturing technologies in firms within Taiwan’s IC packaging industry. Our study will determine the key decision-making factors affecting R&D project selection using FANP, and additionally we develop an optimal manufacturing process. As a case study, the ongoing “Controller IC packaging R&D project A” was chosen to minimize warpage of controller IC.

A failure criterion for debonding initiation between molding compounds and copper leadframes in plastic encapsulated integrated circuit (IC) packages is proposed. The leadframe pull-out test is used to evaluate the bond strengths between molding compounds and leadframes in plastic encapsulated IC packages. The normal and shear stress fields along the interface are analyzed using the finite element method. An average stress approach is employed for the interface failure criterion and the tensile and shear interface bond strengths are obtained from the experimental failure loads. In a parametric study, the effects of specimen loading geometry, moisture, and surface contamination of copper leadframes on the interfacial bond strengths are specifically analyzed. The results show that the interface bond strengths determined for the two specimen geometries are consistent.

Simulation optimization can be used to solve many complex optimization problems in automation applications such as job scheduling and inventory control. We propose a new framework to perform efficient simulation optimization when simulation models with different fidelity levels are available. The framework consists of two novel methodologies: ordinal transformation (OT) and optimal sampling (OS). The OT methodology uses the low-fidelity simulations to transform the original solution space into an ordinal space that encapsulates useful information from the low-fidelity model. The OS methodology efficiently uses high-fidelity simulations to sample the transformed space in search of the optimal solution. Through theoretical analysis and numerical experiments, we demonstrate the promising performance of the multi-fidelity optimization with ordinal transformation and optimal sampling (MO2TOS) framework.

In the integrated circuit (IC) packaging process, including operations of die sawing, die bonding, wire bonding, molding, plating, marking, trim/form, and inspection. Purposes of packaging include protecting ICs, making ICs easier to handle, and connecting ICs to the circuit outside. The wire bond stations are the bottleneck in the packaging and assemble process where the heat block is the key auxiliary parts in the stations. This research proposes a RFID-enabled Heat Block Management System (RHMS) to accurately control the progress of the IC packaging production line to meet the customer requirements. Our research analyzed all the flows of heat block management operations during before and after introducing RHMS. Hypothesis testing can verify significant difference between two sample sizes. Based on the statistics test of hypothesis, we compared the difference for before and after introducing RHMS. The results show that the RHMS can bring advantage for heat block management in wire bond stations. Moreover, it has clear improvement of saving counting and revising operation time. The contributions of this research are not only a case study but also a direction for applying RFID technology on IC packaging industry.

This article discusses configurations of light-emitting diode (LED) light sources for visual inspection of integrated circuit (IC) packages. A package visual inspection (PVI) system with multiple LED light sources used for inspection of IC packages was designed. The image contrast changes of the sample IC packages are explained using the Torrance-Sparrow (TS) model. A few conclusions on appropriate lighting configurations for inspection of various IC packages are achieved. The TS model can be used to represent the specular lobe component. The contrast between two surfaces with different surface roughness values increases with increasing θ i (incident light angle). Lighting C (θ i = 75°) is recommended for packages with high surface roughness heights and resin materials. Lighting B (θ i = 60°) is recommended for packages with moderate surface roughness heights and metal materials. If the background is white, the use of light sources A (θ i = 15°) and B simultaneously is recommended. Light sources A and C are recommended to be chosen for packages with low surface roughness values and transparent materials. The experimental results with the actual gray-level values of the images are compared to support the conclusions. The PVI system is part of an inspection machine. All images of the sample IC packages reported in this article were obtained from an actual production line. Therefore, the results are close to those of the actual inspection situation in the manufacturing industry.

The integrated circuit (IC) industry in Taiwan is comprised mainly of IC chip design and fabrication, IC packaging, and system product design and fabrication industries. Fueled by rapid investment and development efforts from government and private sectors, this industry has sustained a rapid growth in recent years becoming one of the most profitable industries among Asian Pacific countries. This paper details Taiwan's IC packaging manufacturing capabilities and its technology trends. It describes the Taiwan IC package industry's ability to maintain favorable competitive leverage in the global business environment. This paper concentrates on two key areas of manufacturing and technology trends to illustrate Taiwan's electronic industry in general: chip-level packages and substrate and its assembly. The requirements for different applications in the future packages are discussed. The reason for the packaging paradigm shifts and associated precautions are also explained.

The miniature heat sink is an essential component in integrated circuit packaging, playing a vital role in ensuring the stable and reliable performance of integrated circuits. In this paper, we establish a simulation model of the heat transfer performance of a miniature heat sink with a square columnar array microstructure and study the effect of the dimensional parameters of the miniature heat sink on the heat transfer performance. Then, the mathematical equations between the heat source temperature and the dimensional parameters of the miniature heat sink are obtained based on the response surface method, and the dimensional parameters are optimized. Finally, wire electrical discharge machining (WEDM) was used to prepare miniature heat sinks and to test the heat transfer performance. The experimental results show that both the simulation model and the mathematical equations have high accuracy, and the heat source temperature of the miniature heat sink with column width, column distance, and column height of 364 μm, 331 μm, and 1500 μm, respectively, can be reduced to 101.8 °C, which is 93.5 °C lower than the heat source temperature of 195.3 °C without heat sink, and the temperature reduction reaches 47.9%. The miniature heat sink has a simple manufacturing process, low manufacturing cost, small overall size, and good heat transfer performance, which has a broad application prospect in the field of integrated circuit packaging.

The ever increasing demand for fast computing has led to heterogeneous integration of packages as can be seen in the latest Xeon family segments in the market. Microprocessors are now adjacent to memory chips, transceivers, field-programmable gate arrays, and even other microprocessors within a single substrate. These complex designs have instigated an increase in cooling demand for microprocessors, and hence, there has been an increased focus within the semiconductor industry on developing advance thermal solutions. From the packaging level, thermal interface materials (TIMs) play a key role in thermally connecting various components within the package and helps reduce the thermal resistance between the die surfaces and integrated heat spreaders. From the system level, cooling technology is critical to attain the desired overall thermal dissipation and performance. In this review, progress made in the area of TIMs and system cooling solutions are presented. The focus is on the evolution of TIMs and cooling technologies and their challenges in the integrated circuit packaging. Merits and demerits of various TIM materials available in the commercial market are also discussed. The article will be concluded with some directions for the future that would be potentially very beneficial.

This paper presents the development of a nondestructive evaluation method for delamination detection in integrated circuit (IC) packages. The developed method allows for quantitative detection of sealant delamination between integrated heat sink (IHS) and substrate, which is considered a potential failure mechanism in IC packages. The proposed method is expected to overcome the destructive nature of most existing techniques, while maintaining low cost of development. The reported development consists of the following processes: First, flash thermographic analysis is investigated and shown to be incapable of detecting a realistic sealant delamination. Then, ultrasonic guided waves (UGWs) are used as the chosen interrogation method due to their sensitivity to small-size damage and structural thickness variations. The complexity of the received ultrasonic signals caused by the geometric heterogeneity is resolved using a time–frequency signal processing technique. The extracted ultrasonic information, including time-of-arrival (TOA) and amplitude of wave modes received from different sensing paths under multiple excitation frequencies, is then used to construct a feature space. A multivariate Gaussian model is implemented as an information fusion and delamination detection tool, which investigates the distribution of feature space including correlations between features. Results from the developed model are compared with two existing evaluation methods, including pullout force measurement and a delamination metric. The developed method is seen to possess a similar level of accuracy with a nondestructive nature.

The semiconductor industry has been regarded as one of the most important industries by Taiwan due to the market share of Taiwan’s semiconductor industry in 2011 ranked second worldwide. However, the European debt crisis triggered a global economic recession in 2011, causing Taiwan’s output of semiconductors in 2010 and 2011 to show negative growth. This paper will mainly explore, from the performance evaluation perspective, the Malmquist productivity index of the Taiwan’s semiconductor industry based on a metafrontier approach. The empirical results show that the European debt crisis in 2011 had an impact on Integrated circuit (IC) design companies and IC manufacturing companies, but that there was no influence on IC packaging and testing companies when measuring static efficiency. From the viewpoint of dynamic productivity performance, the paper finds that the main reason for the negative growth of IC packaging and testing companies and IC design companies came from a backward movement in technical change, but the main reason for the negative growth of IC manufacturing companies derived from a decline in pure technical efficiency.

High frequency (HF) applications are nothing new. Nor are the multitudes of materials and processes in electronics dedicated to such applications. But with the rising applications and production volumes associated with 5G, IoT (Internet of Things), autonomous driving, and the like, a whole new emphasis is needed to characterize expected base material performance in terms of its processability. Laser-based manufacturing, and in particular laser via drilling, plays a large role in the interconnect and packaging concepts needed for the typically miniaturized design rules, but given the diversity of materials and laser types that can potentially be employed, some clear results-driven guidelines would be beneficial to manufacturers looking to optimize a cost/quality/throughput balance. In this paper we explore laser-based via drilling applications with base materials intended for use in high frequency end applications. There are several HF base material sets employed in HDI (High Density Interconnect)/ICP (Integrated Circuit Packaging) manufacturing, each with their own range of bandwidth and applicable dielectric constant. However, agnostic of the particular material application specifications, the aim of this analysis is to explore potential manufacturing benefits and/or trade-offs for diverse laser/material interactions, while focusing on via-drilling for the HDI and ICP industries in particular. Benefits and trade-offs are characterized by practical and quantifiable elements, precisely: throughput (vias per second), quality (roundness, burr, dimensional integrity, etc). In combination with various laser types, in particular UV (nanosecond), CO2 (microsecond) and green (femtosecond) wavelengths, we analyze the fundamental interaction with materials common to high frequency applications, namely LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), HF FR4, and PI (Polyimide) in an effort to attain practical guidelines for quality and manufacturability. Thus, evidence is provided to potentially increase manufacturing yield with a typically cost-inhibitive material set. Given the, as yet, novel usage of such materials for broadband HDI/ICP applications, this work aims to explore new or re-affirmed baselines suitable to the existing production landscape. Given the broad scope of potential DoE parameters, this work focuses on target via size (75um) applicable to multiple industrial applications, including but not exclusive to, handheld communications, automotive and IoT. Furthermore, the materials is clad with a 12um Cu foil to offer insight into ablation capabilities of each laser type. As a test vehicle default, the vias are drilled in a standard BGA (Ball Grid Array) grid with a pitch of 0.6mm. The results of this work offer-a scored matrix breakdown of our predetermined criteria (throughput, quality) to the laser-material subset analyzed. Given the non-exhaustive nature of this study, the conclusions do not aim to resolve laser-material dilemmas for all forms and factors of high frequency applications and material configurations, but rather offer conclusive evidence that a) high-frequency materials typically require special attention when processing with laser, b) not every laser type works at the same rate of efficiency and efficacy for each of the chosen HF materials and c) a cost/quality balance can be sought by cross referencing results from various laser sources for the intended application.

The development of integrated circuit (IC) packaging is one of the important factors for the advanced production of the semi-conductor industry. With the recent rise of innovative demand of the production technology, lot of issues had been raised at the manufacturing level especially at back-end production. In order to solve the problem, finite element analysis (FEA) is one of the methods that has been broadly used to evaluate the internal stress of IC package. The performance effect of tetrahedral or hexahedral dominance elements in the meshing stage may lead to the unswerving of FEA results. In such condition, the performance of the element type needs to be analyzed in order to determine which implementation leads to result with higher confident level. This study used the quasi-static simulation of FEA to determine the performance of tetrahedral and hexahedral dominance elements in FEA of IC package strength. The monitored stress was focused on the component levels of IC package, the die and the diepad. The IC package is modelled in three-dimensional case which represented as close as the actual product by simplifying certain parts. The performance evaluation had considered the effect of grid independent study for each of the element type. The maximum stress produced by using the tetrahedral element had been compared with the stress produced by the hexahedral dominance elements. Comparison of the performance showed that the value of the maximum stress produced from hexahedral dominance element was significantly higher at 16% to 40% than the solution obtained from the tetrahedral element. It is found that by using hexahedral element in the finite element analysis, a significant higher value of Von Mises stress is produced, which is more than 505 MPa in diepad. This stress value has been established by previous study within the plastic deformation range and also has good agreement with the physical examination.Â

A new method to measure the moisture content of integrated circuit (IC) packages is demonstrated. The moisture contained in the encapsulant resin was determined by using microwaves. The microwave signal was transmitted into the encapsulant resin and reflected at the surface of the chip pad. The amplitude and phase of the reflection coefficient of the microwave signal, which varied with the moisture content of the encapsulant resin, were measured in order to determine the moisture content. A preliminary experiment was carried out, and the calibration equation was developed. The present technique indicates the possibility of determining the moisture content directly without drying and weighing IC packages.

During the solder reflow process, popcorn cracking will occur in integrated circuit (IC) package under vapor pressure and thermal load. Based on the elasticity theory, the singular stress field around the apex of the delaminated interface between die-pad and resin is obtained numerically. The generalized stress intensity factors are computed to evaluate the residual strength of the structure. Also, the structural stability is discussed by using the strain energy density theory. Two factors that are concerned in this paper include the relative stiffness ratio E/sub die-pad//E/sub resin/ and the relative thickness h~. The results show that lower stiffness ratio gives weaker stress singularity. In addition, larger h~ will increase generalized stress intensity factors and structural stability. As a conclusion for our case, moderate value of h~ (say h~=0) is recommended for design.

Influence of solder bump arrangements on molded IC encapsulation