Thermal Interface Materials and Cooling Technologies in Microelectronic Packaging—A Critical Review

High power consumption & high input/out (IO) density are requested by modem electronic components such as high-density electronics, communication satellites, advanced aircraft, networking server and telecommunication devices. Challenges in the heat dissipation of an electronic package arise from the continued increase in power dissipation and power density of higher-power devices. A thermal interface material (TIM) with excellent heat conduction coefficient is applied between the heat source surface and the heat-spreading module. This is to efficiently dissipate heat from the heat source. Thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Therefore, beside the thermal properties, a good mechanical strength of TIM is required. In order to meet demands for higher thermal performance and reliability strength needs in modem electronic devices, various new TIM materials were proposed by industry leading material suppliers. Some of the leading new TIM materials used for this purpose are graphite based and metal based materials where thermal conductivity could be higher than epoxy based TIM materials. In this paper, we will compare new graphite based and metal based TIM materials with existing epoxy based TIM materials and will discuss the various assembly challenges and reliability performance of these new TIM materials. Compare to commercial TIM, the graphite based TIM provide a heat conduction path in a direction perpendicular, metal based TIM is disposed in the Nano-particle metal by sintering to consist of heat conduction path. The junction temperature (Tj) of metal based TIM material shows 5 degrees C decreased than epoxy based material. Also, TIM coverage has been verified via scanning acoustic tomography (SAT) post reliability testing. Moreover, thermal simulations will be conducted and presented in this paper.

The development of high power and compact size semiconductor packages lead to the challenge in the need of high thermal dissipation design. For package level thermal solution, metal (especially copper) heat spreader and metal/metal-oxide filler thermal interface material are widely adopted. However, the thermal performance of packages is limited by isotropic conductive behavior of most of these materials. The thermal conducting performance could be further improved by directing the heat transportation in the direction desired, for instances the in-plane dissipation for heat spreader and the out-of-plane dissipation for thermal interface material. This present study reported the successful adoption of anisotropic thermal conductive pyrolytic graphite sheet as heat spreader and vertically aligned graphite sheet as thermal interface material in semiconductor package, individually. The Joint Electron Device Engineering Council standard still air junction to ambient measurement experiment shows that a flip chip ball grid array package incorporated with a pyrolytic graphite sheet as heat spreader improved thermal resistance of the module by 20%. The thermal dissipation behavior of the module was simulated with a well validated computational thermal dynamics model based on the experimental results. The anisotropic thermal conductive vertically aligned graphite sheet was also adopted as thermal interface material to replace the nowadays grease type thermal interface material. A thermal test chip assembled large size high performance flip chip ball grid array package mounted on a Joint Electron Device Engineering Council defined 4 layers thermal test printed circuit board was chosen as the test vehicle for thermal interface material performance test. The junction to case measurement experiment shows that the package with the anisotropic conductive thermal interface material improved the thermal resistance by 40%. Some novel designs were proposed basing on the application of this anisotropic thermal conductive material as validated by thermal simulation study. Package design guideline basing on the implementation of the anisotropic thermal conductive material will be discussed in this paper.

Minimizing the thermal resistance of thermal interface material (TIM) bondlines is of interest to the electronics industry. The thermal interface material class examined in this study comprises epoxy based adhesives in which conductive filler particles are suspended. When used to assemble a thin bondline (on the order of two hundred microns or less) the apparent thermal conductivity of the bondline has been shown to be less than the bulk thermal conductivity value of the TIM. This deviation is often attributed to inefficient heat transport at the interface between substrate and TIM due to thermophysical mismatches combined with bondline defects including voiding, delamination, and heterogeneous filler distribution in the TIM. Our study focuses on: understanding how various process parameters affect thermal performance and bondline micro structure, and application of standard physics models to understand and optimize TIM bondlines. To this end, we have fabricated TIM bondlines using various TIM materials while systematically varying the process parameters. We employ two different techniques for characterizing the lumped thermal resistance of these bondlines: a micro Fourier apparatus which uses Pt thin film thermometers and a flash diffusivity system coupled to a finite difference parameter estimation algorithm. Our micro Fourier apparatus also includes arrays of Pt thin film thermometers which allow for direct observation of the spatial variations in the temperature. The correlation between these temperature variations and the micro structure of the bondline is studied.

Thermal interface materials (TIMs), consisting of high conductivity filler particles dispersed in a polymer matrix, are used in thermal management of electronics to bridge the gap between the heat generating components and the heat spreader or heat sink. Without TIMs, there is imperfect contact at the interface, resulting in detrimental chip performance and elevated temperatures that can ultimately lead to failure of the chip. In commercial applications, TIMs are dispensed on the chip, heat spreader, or the heat sink using a nozzle via an automated process. The TIM is then squeezed into a thin layer over the substrate by the alternate component (i.e., the device, heat spreader, or the heat sink), often followed by curing (e.g., at elevated temperature) to form a rigid bond. During squeezing, the particle-laden TIM generally exhibits non-Newtonian behavior and, after squeezing, the particle spatial distribution may be non-uniform. The flow behavior depends on dispense pattern (e.g., dots, lines, star patterns), parameters of the squeezing process (e.g., force and squeezing rate), and the TIM composition (e.g., particle shape, size distribution, volume fraction, and matrix composition). The velocity and applied pressure during squeezing significantly impacts the achievable bond line thickness (BLT) and the particle spatial distribution, which can cause the thermal performance of the TIM to deviate from the vendor-specified thermal characteristics. In practice, the maximum allowable squeeze pressure, which impacts the final BLT, is limited by potential mechanical failure of packaged electronics. There are open questions regarding the effect of squeezing on particle rearrangement and its effect on thermal conduction within the particle network. In this work, X-ray micro-computed tomography (XRCT) is used to measure the spatial distribution of particles in the TIM after (a) dispensing and (b) squeezing processes. A mock TIM with a target of 30 vol% copper microspheres (median diameter 114 μm) is created by handmixing the particles with a UV-curable epoxy. Microstructural features such as the average particle volume fraction, coordination number and radial distribution function (RDF) are computed to gain insights into the particle spatial arrangement in the TIM.

In battery packs it is important to know, which temperature the cells have, to avoid overloads and damages. A temperature sensor, which is joined on the battery cell, delivers such data. To guarantee exact temperature measurements on the cell, reliable Thermal Interface Materials (TIM) are needed. They ensure heat transfer from battery cell to the sensor and need to provide good thermal conductivity, moisture independence and adhesion performance under combined environmental loads. For these requirements three different TIM materials were tested and analyzed to determine defects and observing degradation processes under cyclic temperature and moisture loads. Also on focus are the selection guidelines of the correct TIM for different application. The paper describes the characterization of different TIMs, new thermal test cycles combined with moisture and the resulting effects on degradation behavior of TIMs.

Its self-heating process directly affects the optical performance and reliability of light – emitting diodes (LEDs). It is important to disperse the generated heat from LED to surrounding atmosphere and keep the LED light performances same as declared by the manufacturer. Thermal interface material (TIM) is applied in between sink and source to reduce contact resistance at the junction between substrate and heat sink interface of the LED modules. This paper provides an assessment on ‘thermal interface materials’. Here different TIM materials used and the performance and problems of these commercial interface materials are discussed. From this study, one can calculate the temperature distribution in the sink area for different types of TIM materials under thermal conductivity perspective and be able to find the capability of dissipation of heat at the end surfaces of heat sinks, and design their system as well. In another process, TIMs with different thickness and input drive currents for the COB-based LED are investigated by using COMSOL simulation software. The results show that the junction temperature of the LED luminaire increases and reduce the lifetime when the input drive current and thickness of the TIM layers increase.

Study on thermal contact resistance of low melting alloy used as thermal interface material

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

Thermal management problems in electronic packages have been a challenging problem due to increasing number of transistors in chips and reduction in product size. Thermal interface materials (TIM) help heat dissipation by reducing thermal contact resistance between chip and integrated heat spreader (IHS) and TIM quality is critical for effective removal of heat generated from the package. Therefore, identification of defects within TIM is required during package assembly process development. Imaging techniques such as computerized scanning acoustic microscopy (CSAM) and X-ray tomography are used as non-destructive testing techniques to identify TIM defects qualitatively. More recently, it was shown that IR thermography can be used as a qualitative means of identifying defects as well. Thermal diffusion tomography is a powerful alternative to those techniques due to its lower cost and ease of application. In this study, quantitative characterization of defects in TIM is presented using thermal diffusion tomography. The study is conducted considering a high density interconnect flip chip package that includes spreading effect due to different sized IHS and die. Defect size and location are detected analyzing the measured thermal response of electronic package by solving the resulting inverse problem by Levenberg-Marquardt algorithm as an image reconstruction technique.

Thermal interface materials (TIMs) play a critical role in enhancing the efficiency of next-generation packaging technologies within the semiconductor industry.[1] The increasing heat density in the latest transistor node sizes, coupled with the continuous increase in die sizes, presents a significant challenge for TIM1s. Modern TIM1s used in semiconductor packaging must not only offer remarkably low thermal resistances (<5 mm^2·K/W), but also exhibit exceptional mechanical performance to accommodate the significant warpage resulting from coefficient of thermal expansion (CTE) mismatches in the packages. Recently, researchers have proposed the use of liquid metal embedded elastomers (LMEEs) [2] as thermal interface materials [3] to create a TIM based on LMEEs that can meet the demands of the most challenging applications. In this presentation, we offer material-level characterization and thermal test vehicle (TTV) testing of LMEEs. Our findings demonstrate that achieving an ultra-thin bondline thickness on the order of 20 µm allows us to attain an exceptionally low thermal resistance of less than 5 mm^2·K/W between the die and integrated heat spreader (IHS). Furthermore, we provide insights into the interplay between adhesion, stretchability, and modulus of the TIM. These are crucial factors for ensuring the TIM has the necessary mechanical properties to maintain the integrity of the interface between the die and the heat sink, thus preventing any degradation in thermal resistance following thermal shock tests. In the end, we present data on the in-situ changes in thermal resistance of LMEEs as a function of strain while cured between two silicon dies, shedding light on the thermomechanical behavior of LMEEs.

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface. This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process. The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area. Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.

In the 5G era, the high performance computing (HPC) products play a pivotal role in supporting big data computing, data center transmission and networking applications. For computing performance enhancement, there are two development trends of product design including chip integration and high thermal dissipation. First, integrating the high bandwidth memory (HBM) into the package is a way to achieve both short and high-speed data transmission. In industry, fan-out platform can provide the benefit for die to die interconnection with fine line and the fine pitch bump design. Second, HPC devices bring high power consumption and require a thermal interface material (TIM) with high thermal conductivity for junction temperature reduction of SoC chip, due to the higher junction temperature will have work fail risk of SoC and even affect the nearby HBM. For high thermal TIM, the thermal conductivity of graphite TIM is directional, XY and Z axis are around 10W/mK and 20W/mK, respectively. The heat dissipation are not only through the vertical direction but also partially through the horizontal direction to the surroundings. The outstanding vertical thermal conductivity can effectively reduce the heat from SoC hot spot and reduce the thermal impact on HBM.Compared with normal FCBGA platform, a way to evaluate graphite TIM in FO structure is provided in this study. The maximum junction temperature impact of SoC and HBM is being explored from thermal simulation between different SoC hot spot design including uniform, center and corner conditions. In addition, the top exposed surface of chip module includes multiple interface with silicon and epoxy molding compound (EMC). We address the graphite TIM attaching performance and TIM coverage. Furthermore, through the innovative structure design to add the adhesive around the chip module, TIM coverage can be improved, especially for large package with worse warpage. All of the silicon die, EMC and underfill are pass without crack from SEM inspection, even if a larger HS (Heat Spreader) clamping force is required for graphite TIM. Finally, we have finished and passed the PLR (Package Level Reliability) with temperature cycle test (TCT) and unbiased highly accelerated stress test (uHAST) conditions.

Ensuring adequate thermal performance is essential for the reliable operation of flip-chip electronic packages. Thermal interface materials (TIMs), applied between the die and a heat spreader form a crucial thermal junction between the first level package and external cooling mechanisms such as heat-sinks and cooling fans. Selection of a good TIM is dependent not only on its thermal properties but also on its ability to withstand mechanical stresses in an electronic package. In the past, FEM models have been applied to obtain the stresses and strains in the TIM using time-independent analysis. However, there has only been limited work in extending these models to predict the damage (both mechanical and thermal) in a TIM during thermo-cyclic loading. Our current work presents a technique to predict the thermal damage in TIMs over cyclic loading. Calibrated finite element analysis models have been created to predict accurate TIM strains in thermal test-vehicles. These predicted mechanical strains are then correlated with experimentally observed thermal degradation and finally, a phenomenological model is developed which predicts the thermal performance of an electronic package during cyclic loading.

Historically, for semiconductors subject to standard operating temperatures--which tend not to exceed 125°C--the Tg (glass transition temperatures) of the organic packaging materials protecting the chips is usually around 175°C. Given that, when it comes to electronics operating at high temperatures—typically an environment where the ambient temperature exceeds 200°C—the use of organic materials is generally prohibited due to rapid degradation. At those elevated temperatures, the packaging materials selected are generally composed of metals and ceramics but these materials come with their own shortfalls as well as higher material and manufacturing costs. Therefore, it would be desirable if there were ‘ruggedized’ versions of the organic compounds so commonly used in semiconductor packaging but available for more extreme temperatures, both to reduce cost and package footprint. Meanwhile, the demands from recent developments in high performance computing (HPC) and high-speed data networks means a greater need for increased power and thermal dissipation coupled with very large package body sizes to accommodate the high I/O count. The latest in server microprocessor (MPU) products can easily generate up to 300W during operation, and the heat generated must be quickly transported away from chip to prevent the threat of thermal shutdown. The thermal dissipation issue is controlled by the use of heat spreaders and heat sinks, both of which are intended to make contact with the back-side of a flipped MPU via a thermal interface material (TIM), as part of a large die, large body-size flip-chip ball grid array (FCBGA) package. The thermal interface materials discussed here are examples of organic engineered materials that are capable of withstanding higher operating temperatures than typically seen by semiconductors encased in organic-based packaging. This paper will look at the key material and mechanical attributes for a good thermal interface material, examines the pros-and-cons of various thermal interface material formulations, and discusses the factors for reliable thermal dissipation performance.

A thermal interface material (TIM) with the highest thermal conductivity does not automatically deliver the best thermal management performance. It is just as important to achieve the best surface contact between TIM and various substrates. Softer interface materials like silicone gap fillers tend to lower contact resistance and thermal impedance. More importantly, the low modulus of silicone gap fillers also decreases the stress due to the large mismatch of the coefficient of thermal expansion (CTE) in microelectronic packages with die chips, heat sinks, heat spreaders, and substrates. However, decreasing the modulus of the gap fillers is often associated with increased creep behavior under compression as well as poor recovery upon removal of the stress. The desired thermal gap fillers must remain elastic at low temperatures and keep thermal stability at high temperatures while still maintaining good thermal conductivity. For the investigation described herein, DMA (Dynamic Mechanical Analysis) was used to characterize the viscoelastic creep and stress relaxation properties of silicone gap fillers at various conditions. New thermal gap fillers using silicone chemistry were developed for this study to provide low modulus and high elasticity and were investigated along with commercially available silicone gap fillers. Thermal impedance properties at different operating conditions such as during long term exposure for elevated temperatures and humidity were also monitored with corresponding thermo-mechanical properties in DMA.