Using distortion shaping technique to equalize ADC THD performance between ATEs

This paper presents deeply analysis and comparison of different modulation techniques for the modular multilevel converter without using arm inductor. In case of PWM, losses are more and Total Harmonic Distortion (THD) performance is very poor. With the introduction of delta modulation in MMC, the losses will reduce and THD will improve. It can be seen that the THD is 4.9% for delta modulation and 3.82% for adaptive delta modulation without using arm inductance but THD is 13.15% for delta modulation with arm inductance. It means THD has been improved without using arm inductance. It has been observed that the adaptive delta modulation has better THD response as compared to delta modulation due to its several advantages. The THD performance has been calculated and mentioned at different modulation indexes. It has been also observed that the THD performance is better with delta and adaptive delta modulation.

Comprehensive waveform generation is an important functional component of automated test equipment (ATE). Waveform generators synthesize signal stimuli to be applied to a device under test (DUT). As military and commercial electronics become increasingly complex, more sophisticated signal stimuli are required. ATE requires signal stimuli varying from advanced communication signals to the playback of captured real-world analog signals. Waveform generators can synthesize signals that can be broadly categorized into four types: standard functions, advanced functions, arbitrary waveforms, and waveform sequences. Standard functions include the simple sine, square, triangle, pulse, and ramp waveforms. Advanced functions include complex signals such as multi-tone, AM, FM, sinc pulse, haversine, half-cycle sine, Gaussian pulse, Lorentz pulse, noise and others. Arbitrary waveforms involve the point-by-point user-defined waveform synthesis. Waveform sequences provide a mechanism to piece together standard or arbitrary waveforms in stages to create a user-defined compound waveform. Example applications for each of these four waveform categories are described in this paper. Modern waveform generators are extremely powerful, but can also add significant complexity for the user. The arbitrary waveform generator, an instrument found in most ATE systems, is a very powerful signal synthesis tool. Unfortunately, many users take advantage of only a small fraction of the powerful features available to them in an arbitrary waveform generator. Also, selecting the right arbitrary waveform generator can be daunting when comparing specifications such as DAC resolution, clock rates and topology, memory depth, sequencing, sweeping, triggering and synchronization. This paper describes the technical differences between various signal generation techniques, presents the signal fidelity impact of clock topology, discusses dynamic range limitations due to noise, accuracy and resolution, and provides typical applications to illustrate signal generation usage. Ultimately, this information should help the user avoid common pitfalls in applying waveform generators within ATE.

Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.

The Arbitrary Waveform Generator (AWG) is an important instrument that is widely used in automatic test equipment, radar system, and other fields for generating complex signals. The increasing demand for waveform's complexity is consisted of repeatable segments and advanced-segments, where each segment or segments group could be repeated multiple times. Those requirements make the existing design, implemented by an address generator, complex. The software defined technology can separate the instruction sequence processing from the Data plane to the Controller where the complex logic is defined by software, which lead to a simplified data plane. This paper proposes a design that will generate complex arbitrary waveform by decoupling the waveform composing logic in address generator out from the data plane as an instruction controller. The controller support instruction sequence defined by segment and a jump instruction, which can implement the repeatable segments and the advanced-segments, respectively. We built an AWG based on this design and made the implementation in a field programmable gate array with a required clock frequency of 125 MHz. The design has a high sampling rate of 4 gigabit samples per second and can generate complex arbitrary waveform consisting of repeatable segments and advanced-segments.

This paper presents the mathematical and harmonic analyses of output phase voltages of three-phase voltage source inverters which employ a hybrid two-dimensional-three-dimensional (2-D-3-D) space vector modulation (SVM) voltage control algorithm. The explicit time-domain representation of the harmonic components in addition to the total harmonic distortion (THD) of the output phase voltages is given in terms of system and control parameters. This paper also investigates the harmonic characteristics and THD performance against the linearity of the modulation region which helps in the harmonic performance and design studies of such inverters employing the hybrid 2-D-3-D SVM. The fundamental component of the output voltages follows the reference with lower THD in the linear modulation region rather than the overmodulation region. Experimental results are used to validate these analyses as well as the effectiveness of the hybrid 2-D-3-D SVM algorithm for generating balanced and low THD phase voltages.

The purpose of this paper is to present a framework from which Automated Test Equipment (ATE) manufacturers can use to help them develop, integrate, and deliver ATE cloud-based applications to the consumers of their products. In order to create these applications, the developer can utilize Commercial Web Services (CWS) as a means to help access compute power, storage devices, and other services that provide the flexibility to choose a development platform or programming model that makes the most sense in trying to resolve the problem at hand. CWS provides a flexible environment from which to choose various programming models, operating systems, databases, and architectures to serve the consumers needs. CWS is highly cost-effective in that the developers and consumers pay only for what they use. Using CWS makes it extremely easy to create scalable and elastic systems as the developers can quickly add and subtract resources to their applications in order to meet current or future consumer needs. Furthermore, security is always a concern so CWS builds services in accordance with security best practices by providing the appropriate security features in those services. Using a CWS provides a level of scale, security, reliability, and privacy that are often cost prohibitive for most organizations to meet. This paper will examine available CWS cloud service platforms that organizations can potentially use to help deploy applications and services in a cost effective manner. The CWS platform consists of the following six main services, which will be discussed in more detail in this paper - (1) Computational/Networking, (2) Storage/Content Delivery, (3) Databases, (4) Analytics, (5) Applications, and (6) Deployment and Management services. One or more of these services may be utilized to help develop, integrate, and deliver ATE cloud-based applications to the consumer. The goals of ATE are to (1) quickly and accurately detect and isolate each fault, (2) provide software tools for analyzing historical data, (3) gather, manage, and distribute accurate and reliable maintenance information for the failed Unit Under Test (UUT). The CWS cloud platform will aid in the development of cloud based tools and applications that are cost effective, flexible, scalable, and secure that can be used by multiple end users to aid in the development of ATE system software tool sets. One example of a cloud-based application is a diagnostic reasoner that could be used to aid in diagnosing UUT repair actions. This paper will show how developers can use CWS to develop ATE cloud-based applications and tools that will help improve the overall ATE testing throughput, thus resulting in bottom line improvements to ATE life cycle costs.

Focus on test and measurement

We are developing an arbitrary waveform generator (AWG) to provide enhanced capability for radar applications. The current design accommodates two waveform generators on a single unit for dual frequency operation. The basic architecture of this unit employs a field programmable gate array (FPGA) and a high speed and high precision digital to analog converter (DAC) for direct digital synthesis. This AWG is capable of up to 450 MHz bandwidth with ability for frequency notching. Phase fidelity of better than 1.2/spl deg/ deviation RMS is also achievable. This AWG operates with lower power consumption as compared with other waveform generators, which is advantageous for future spaceborne applications. This will enable radars to return higher precision data, to be reduced in complexity, and to operate in any band without interfering with dedicated bandwidths.

An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.

This research project aims to expand the capability of current US Navy Automated Test Equipment (ATE) family of testers known as the Consolidated Automated Support System (CASS). Industry research is now focused on breaking the historical construct of test equipment. Advances in the field of Synthetic Instruments have opened the door to test avionics in new ways. Every year new capabilities are developed using core hardware and increasingly capable software modules to create complex waveforms. This research creates a Digital Radio Frequency Memory (DRFM) Synthetic Instrument that can be programmed to perform a wide array of low latency Radio Frequency (RF) tests. Synthetic Instruments are defined as a concatenation of hardware and software modules used in combination to emulate a traditional piece of electronic instrumentation. This Synthetic Instrument couples high speed Analog-to-Digital Converters (ADC) to high speed Digital-to-Analog Converters (DAC) with Field Programmable Gate Arrays (FPGA) in between for digital signal processing. An RF front end is used to down convert the RF to baseband where it is sampled, modified, and up converted back to RF. The FPGA performs Digital Signal Processing (DSP) on the signal to achieve the desired output. Application of this DRFM in automated testing is demonstrated using a Reconfigurable Transportable Consolidated Automated Support System (RTCASS) tester at Naval Air Systems Command (NAVAIR) Jacksonville, FL. The Unit Under Test (UUT) is an ALQ-162 Defensive Electronic Countermeasures (DECM) receiver-transmitter. Ultra-low latency signals are generated to simulate enemy jamming stimulus. As the ALQ-162 detects and responds to the input, the DRFM switches to a new frequency. The time taken by the ALQ-162 to acquire, respond, and re-acquire is measured. This test confirms the internal Yttrium Iron Garnet (YIG) oscillator meets slew specifications. Currently Navy ATE can only test RF units using high latency steady state tests. This research project developed a supplemental unit that can be added to the VXI chassis in the CASS family of testers and conduct ultra-low latency active tests. The instrument acts as hardware-in-the-loop to perform real-time tests including a new capability to measure jamming response time from DECM avionics. Demonstrated performance capabilities include: latency <; 100 ns, output Spurious-Free Dynamic Range (SFDR) > 80 dBc, input SFDR > 60 dBc, frequency tuning resolution <; 2 Hz, and frequency settling time <; 0.5 ns. New RF capabilities developed by this effort parallel similar research ongoing for digital test instruments like the Teradyne High Speed Subsystem. Incorporating this Digital RF Memory synthetic instrument into current and future ATE will improve readiness and supportability of the fleet. Improvements demonstrated by this research project will expand the type and quantity of assets able to be tested by current and future ATE.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

This paper presents an arbitrary waveform generator (AWG) based on field-programmable-gate-array (FPGA) technology and a 12 bit digital-to-analog converter (DAC). It has a user interface with a PS/2 keyboard and a 16×2 character LCD display. The system is mounted on a printed circuit board which includes the DAC and analog amplification stages. This device has been developed as part of a system for laboratory experiments for ultrafast scan voltammetry (UFSV).

DAC-board based X-band EPR spectrometer with arbitrary waveform control

Traditionally, automated test equipment (ATE) manufacturers have been producing test systems to meet the needs of the electronic industry and research organizations. There is however another fairly large ATE market that has not been addressed by ATE-educational institutes and universities. Issues related to the electronic test equipment for educational institutions are discussed in this paper. It identifies the requirements to implement a test engineering program in the university environment, the challenges that face both university and industry, and strategies that can be adopted to meet these requirements. It provides a general roadmap that allows customization to suit emerging test engineering developments that may occur future. Consideration is given to a pragmatic, and cost effective collaboration between the academic and industrial worlds.

This study proposed a novel Field Programmable Gate Array (FPGA)-based 32-channel data acquisition system to acquire and process Electroencephalography (EEG) signal. The data acquisition system utilized PYNQ-Z1 board, which was equipped with a Xilinx ZYNQ XC7Z020-1CLG400C All Programmable System-on-Chip (APSoCs) that offered high performance embedded system because of the combination between the flexibility and versatility of the programmable logic (PL) and the high-speed embedded processor or programmable system (PS). As the core of the data acquisition system, the FPGA collected, processed, and stored the data based on Front-End Analog to Digital Converter (ADC) ADS1299EEG-FE. The communication protocol used in the data acquisition system was Serial Peripheral Interface (SPI) with daisy-chain configuration. For the signal processing part, a 5th-order Butterworth bandpass filter and Fast Fourier Transform (FFT) has been implemented directly on the PYNQ’s Overlay. The overlay was configurable FPGA design that extend the system from the PS of the ZYNQ to the PL, enabling us to control directly the hardware platform using Python running in the PS. The mean accuracy error obtained from validation result of the developed system was 1.34% and the Total Harmonic Distortion (THD) performance criterion resulting in 0.0091%, both of them validated with NETECH MiniSIM EEG Simulator 330. The comparison between the developed system and Neurostyle NS-EEG-D1 System acquiring the same EEG data shows correlation parameter gradient of 0.9818, y-intercept with -0.1803, and R squared of 0.9742 based on the least square analysis. The parameter above indicated that the developed system was adequate enough, if not on a par, with the commercialized, medical grade EEG data acquisition system Neurostyle NS-EEG-D1 as the system assured and maintained accuracy with higher sampling frequency.