A digital calibration technique for multi-bit-per-stage pipelined ADC

This paper presents a novel methodology for the design and calibration of ultra-compact digital-to-analog converters (DACs), integrating architectural redundancy and a digital calibration algorithm. The proposed calibration approach generates pre-distortion codes that correct both positive and negative nonlinearity errors, even in designs with severe mismatch or relaxed layout constraints. This enables the use of aggressively scaled devices while maintaining high linearity and spectral fidelity. The algorithm is architecture-agnostic and compatible with resistor-string, current-steering, and hybrid DAC structures. It operates with minimal memory, low latency, and supports both foreground and background calibration modes. The method is validated through simulation and silicon measurement of three 14-bit DAC architectures fabricated in TSMC 180 nm CMOS. Post-calibration results demonstrate linearity within ±0.5–1.2 LSB, ENOB up to 13.8 bits, and significant improvements in SNR, SFDR, and THD. The compact layouts—occupying as little as 0.0169 mm2—highlight the scalability of the proposed method for applications such as analog AI accelerators and high-density mixed-signal SoCs.

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about $1.5\,\, {\times } \,\, 10^{6}$ samples for the calibration of five stages.

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

The performance of a wideband receiver is highly dependent on the performance of the analogue‐to‐digital converter (ADC) used. Such applications require ADCs to operate at ultra‐high speeds with high accuracy for inputs ranging from 40 MHz ‐ 1 GHz. Conventional solutions either use filters and mixers to extract the frequency of interest and convert it using a low‐speed ADC or use a single ultra‐high‐speed flash converter. Both of these solutions consume ultra‐high power and require complex circuitry, which expands exponentially with the converter resolution. In this work, a 12 bit 3.072 GS/s time‐interleaved pipeline ADC is proposed. In total, 32 pipeline ADCs, each with a sampling rate of 96 MS/s, are interleaved in the time domain to achieve an overall sampling rate of 3.072 GS/s. In addition to the potential energy‐saving capabilities of a time‐interleaving structure, the circuit adopts amplifier sharing in sample‐and‐hold circuits, further improving the power efficiency. To account for interleaving mismatch, the circuit uses a pure background calibration technique, maintaining the system linearity and spectral efficiency. The proposed design achieves signal‐to‐noise‐and‐distortion ratio of 53.65 dB and spurious‐free dynamic range (SFDR) of 69.04 dB while consuming 820 mW of power at a 1.2 V supply, resulting in a figure‐of‐merit of 0.67 pJ/conv‐step.

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digital circuits, and is applicable to both single-bit and multibit-per-stage architectures. Simulations with a 15-stage, 1.5-bit-per-stage pipelined ADC with capacitor mismatch of sigma = 0.25% in each stage show that the technique improves signal-to-noise-distortion ratio from 62 dB (10 bits) to 94 dB (15.4 bits).

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-V P-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.

In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing code elimination. It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both the static and dynamic performance.

An analytic appraoch is presented for estimating the nonlinearity of an analog to digital converter (ADC) as a function of the variations in the circuit devices. The approach is demonstrated for the case of a pipeline ADC with digital error correction. Under some mild assumptions on the expected variations, the error probability is expressed as a simple explicit function of the standard deviations in the components' parameters: gain errors, comparator offset errors and resistor errors. The analytical expression is verified for Integral Non Linearity (INL), and its limits are studied using Monte-Carlo simulations of a 10 bit pipeline ADC structure.

The design of a 10-bit, 200MS/s Pipelined Analog to Digital Converter (ADC) is presented in this paper. The implemented pipelined ADC employs techniques such as pipeline stage scaling algorithm, to lower power, capacitor ratio independent conversion scheme, a nested gain boosting technique and thin oxide transistors with clock bootstrapping. The fully realized is measured under different input frequencies with a sampling rate of 200MS/s and it consumes 46.8mW from a 1.8V power supply. The pipelined ADC implemented in 130nm CMOS technology exhibits signal-to-noise plus distortion ration SNDR of 54.7dB and occupies a die area of 0.31mm2.

This paper presents a digital domain foreground calibration algorithm for flash analog-to-digital converters (ADC). In deep sub-micron technologies, for low voltage and low power applications, random mismatch appearing in comparator circuits induce large offset voltages. The linearity of a flash ADC gets adversely affected by the offset voltages. In the proposed method, a lookup table (LUT) based offset calibration technique has been introduced to nullify the effect of comparator offset voltages to improve the linearity of the flash ADC. Behavioural simulation result of a 6 bit flash ADC shows that after calibration SNDR gets improved from 28.01 dB to 33.23 dB.

Design of low-voltage high-resolution MOSFET-only pipeline analog to digital converters (ADCs) has been investigated in this work. The nonlinearity caused by replacing linear MIM capacitors with compensated depletion-mode MOS transistors in all 1.5-bit residue stages of the ADC has been properly modeled to be calibrated in digital domain. The proposed calibration technique makes it possible to digitally compensate the nonlinearity of a 1.8V 12-bit 65MS/s MOSFET-only ADC in 0.18 mum standard digital CMOS technology. It improves the values of signal-to-noise-plus-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) by approximately 27dB and 35dB respectively

A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR

A zero-crossing-based circuit (ZCBC) is a promising technique for low-power high-resolution pipeline analog-to-digital converters (ADCs). Unfortunately, operating ZCBC ADCs at high speeds near 1 GS/s is quite challenging due to the delay of the zero-crossing detector that introduces nonlinear gain and offset errors. To solve nonlinearity, we propose a ZCBC pipeline ADC that employs a passive resistor as a current source. Due to its inherent linearity, the resistor-based ZCBC eliminates the input dependency of the interstage gain and offset errors, allowing a simple calibration. Furthermore, a background offset calibration scheme is proposed to cope with the large offset that results from high-speed operation. A prototype ADC implemented in 65-nm CMOS achieves an SNDR/SFDR of 47.26/62.64 dB at 1 GS/s while consuming 46.52 mW from 1 V supply.