Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about $1.5\,\, {\times } \,\, 10^{6}$ samples for the calibration of five stages.

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

The performance of a wideband receiver is highly dependent on the performance of the analogue‐to‐digital converter (ADC) used. Such applications require ADCs to operate at ultra‐high speeds with high accuracy for inputs ranging from 40 MHz ‐ 1 GHz. Conventional solutions either use filters and mixers to extract the frequency of interest and convert it using a low‐speed ADC or use a single ultra‐high‐speed flash converter. Both of these solutions consume ultra‐high power and require complex circuitry, which expands exponentially with the converter resolution. In this work, a 12 bit 3.072 GS/s time‐interleaved pipeline ADC is proposed. In total, 32 pipeline ADCs, each with a sampling rate of 96 MS/s, are interleaved in the time domain to achieve an overall sampling rate of 3.072 GS/s. In addition to the potential energy‐saving capabilities of a time‐interleaving structure, the circuit adopts amplifier sharing in sample‐and‐hold circuits, further improving the power efficiency. To account for interleaving mismatch, the circuit uses a pure background calibration technique, maintaining the system linearity and spectral efficiency. The proposed design achieves signal‐to‐noise‐and‐distortion ratio of 53.65 dB and spurious‐free dynamic range (SFDR) of 69.04 dB while consuming 820 mW of power at a 1.2 V supply, resulting in a figure‐of‐merit of 0.67 pJ/conv‐step.

In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing code elimination. It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both the static and dynamic performance.

In this paper a new digital background calibration method for successive approximation register analog to digital converters is presented. For developing, a perturbation signal is added and also digital offset is injected. One of the main advantages of this work is that it is completely digitally and eliminates the nonlinear errors between analog capacitor and array capacitors due to converter’s capacitors mismatch error by correcting the relative weights. Performing of this digital dithering method does not require extra capacitors or double independent converters and it will eliminate mismatches caused by these added elements. Also, No extra calibration overhead for complicated mathematical calculation is needed. It unlike split calibration, does not need two independent converters for production of two specified paths and it just have one capacitor array which makes it possible with simple architecture. Furthermore, to improve DNL and INL and correct the missing code error, sub radix-2 is used in the converter structure. Proposed calibration method is implemented by a 10 bit, 1.87-radix SAR converter. Simulation results with MATLAB software show great improvement in static and dynamic characteristics in applied analog to digital converter after calibration. So, it can be used in calibration of successive approximation register analog to digital converters.

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.

This paper presents a fast background digital calibration method for pipelined analog-to-digital converters (ADCs) that is robust and converges fast. To avoid the problem of input signal amplitude limitation, the proposed calibration technique takes advantage of the digital redundancy architecture by injecting pseudo-random noise (PN) in the sub-ADC. A split ADC architecture combined with a switch array control unit is also proposed to minimize the correlation between the input signal and the injecting PN signal. Simulation result shows, when the capacitor error is 0.1%, and the gain error between the two channel is 1%, the calibration time is about 217 samples simulated with 15-bit accuracy with a 0.32/−0.33 LSB DNL and a 0.50/−0.24 LSB INL, and the SNDR is 91.5 dB, the SFDR is 110.3 dB.

In this paper, a digital calibration algorithm, based on original radix 2 off-line algorithm, is employed to calibrate a 4 stages, 12 bits pipelined Analog-to-Digital Converter(ADC). The detail implementation process of this algorithm, from algorithm design to circuit structure, is presented. The simulation results show that the calibrated ADC achieves SNR of 73.9 dB, SNDR of 73.3 dB, SFDR of 84.2 dB, DNL of 0.47 LSB and INL of 0.84 LSB.

A new digital background calibration technique to compensate the capacitor mismatch in pipelined analog-to-digital converters (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to global gain error. A simple modification to the conventional MDAC allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC. This method does not produce any limitation of the ADC in terms of speed or input dynamic range.

The paper deals with a novel 12-bit low power switched-capacitor (SC) pipelined analog-to-digital converter (ADC). The problems caused by using of SC technique are compensated or roughly attenuated by means of combination of well-known analog-domain techniques and new digital background calibration technique. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches the fully differential circuitry was utilized. The special op-amps and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the op-amps was taken into account too. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

An analytic appraoch is presented for estimating the nonlinearity of an analog to digital converter (ADC) as a function of the variations in the circuit devices. The approach is demonstrated for the case of a pipeline ADC with digital error correction. Under some mild assumptions on the expected variations, the error probability is expressed as a simple explicit function of the standard deviations in the components' parameters: gain errors, comparator offset errors and resistor errors. The analytical expression is verified for Integral Non Linearity (INL), and its limits are studied using Monte-Carlo simulations of a 10 bit pipeline ADC structure.

The design of a 10-bit, 200MS/s Pipelined Analog to Digital Converter (ADC) is presented in this paper. The implemented pipelined ADC employs techniques such as pipeline stage scaling algorithm, to lower power, capacitor ratio independent conversion scheme, a nested gain boosting technique and thin oxide transistors with clock bootstrapping. The fully realized is measured under different input frequencies with a sampling rate of 200MS/s and it consumes 46.8mW from a 1.8V power supply. The pipelined ADC implemented in 130nm CMOS technology exhibits signal-to-noise plus distortion ration SNDR of 54.7dB and occupies a die area of 0.31mm2.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-V P-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.