A New Calibration Method for SAR Analog-to-Digital Converters Based on All Digital Dithering

Several integrated capacitors can be used in analog-to-digital converters (ADCs) for complementary-metal-oxide-semiconductor (CMOS) image sensors, including metal-insulator-metal (MIM), metal-oxide-metal (MOM) and metal-oxide-semiconductor (MOS) capacitors. Among those capacitors, MOS capacitors have the highest capacitance density per unit area but a large voltage dependency, which will cause the non-linearity of ADCs. Recently, several types of ADCs are employed for column-parallel ADCs, including a single-slope (SS), sigma-delta (ΔΣ), successive approximation (SAR) ADC, cyclic ADC and folding-integration/cyclic (FI-Cyclic) ADCs. A Cyclic ADC is well known for its ability to achieve medium resolution while requiring a small silicon area and implementing a reasonable conversion rate of one conversion cycle per bit of resolution. Compared with other ADCs, the cyclic ADC has superiority in overcoming the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise and HDR. On the basis of inheriting the advantage of cyclic ADC, FI-Cyclic ADC has better performance on low noise, high grayscale resolution and resulting high dynamic range.

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/−0.52 least significant bit and +0.62/−0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.

The pulse capacitor charging power supply is a key device in the pulse power technology. To study the higher precision high voltage pulse capacitor charging power supply, the paper analyzes the transfer function and its voltage and current transfer characteristics based on a novel double resonance topology. There are two resonance points in the double resonance circuit. According to this characteristic, a frequency modulation control method is proposed. That is, the charging phase and the high voltage holding phase, the first phase adopts the series resonant working mode, and the high voltage holding phase reduces the switching frequency to approach the second resonance point, thereby realizing dynamic compensation of the pulse capacitor self-discharge voltage drop, so that the charging accuracy and a large increase in high voltage stability of pulse capacitance at the same time can be ensured. Based on Matlab/simulink, the simulation model is built to verify the correctness of the frequency modulation method of the proposed dual resonance topology.

In this paper, a low power split capacitor array structure based successive approximation register (SAR) type analog to digital converter (ADC) is proposed. To minimize power, this ADC combines the capacitive digital to analog converter (DAC) with the sample and hold (S/H) circuit, uses the Split binary-weighted capacitor array for the DAC, and utilizes the open-loop comparator. The ADC consumes low power with good performance. The DAC efficiently uses charge recycling to achieve a high speed of operation. The proposed ADC is designed using 0.18-μm CMOS technology. At a 1.8-V supply and 2 MS/s, the ADC achieves a spurious-free dynamic range (SFDR) of 54 dB and consumes 0.27633 mW.

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs' parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.

This Letter presents a 12b-control ultra-low-power low-noise two-stage single-ended to differential switched-capacitor variable gain amplifier (SC-VGA) for 2–6-MHz second harmonic cardiac imaging ultrasound probes in 0.18 μm complementary metal oxide semiconductor. The proposed SC-VGA consists of inverters and capacitor (CAP) arrays. By adopting inverters instead of operational trans-conductance amplifiers (OTAs) in traditional SC-amplifiers, both the power and noise are significantly improved. Each stage has a 6b binary-weighted CAP array, and in total the 12b CAP arrays achieve the dB-in-linear gain range from − 21 to 21 dB. The CAP array is divided between the upper 3b and lower 3b by a CAP to decrease the capacitance spread. The total power consumption is 150 μA at 1 V supply voltage, and the input referred noise is 6.5 nV/√HZ at 4 MHz. The second harmonic distortion (HD2) has the mean value − 77 dB at the 460 mV peak-to-peak output swing for 50 samples of Monte Carlo mismatch simulation with a 30 MHz sampling frequency.

The application of anatase titanium dioxide (TiO2), which is an abundant and cost effective resource, in supercapacitors has been restricted due to its poor electronic conductivity and limited mechanical stability. A biomass-derived carbon was coated on anatase TiO2 nanoparticles via practical and green hydrothermal carbonization in order to overcome these limitations. Hierarchically porous carbon provided a capacitive double layer for charge storage and the TiO2/C nanocomposite exhibited a specific capacitance of 61 F × g-1 (0.25 A × g-1, 0 to 1 V vs. Ag/AgCl, 1 M H2SO4 aqueous electrolyte). The TiO2/C/PEDOT:PSS nanocomposite with enhanced specific capacitance and rate capability (189 F × g-1 at 0.25 A × g-1, 161 F × g-1 at 0.5 A × g-1, 123 F × g-1 at 1 A × g-1, 91 F × g-1 at 2 A × g-1) was obtained by the application of an electrochemically active PEDOT:PSS layer. The prominent electrochemical and mechanical stability of the ternary nanocomposite was demonstrated by its ability to retain 98 % of its initial capacitance after 1500 cycles of charge-discharge at a high current rate (3 A × g-1). The synergistic use of sustainable organic and inorganic components with environmentally friendly and practical methods yields extremely promising electrochemical performances for supercapacitor applications. The TiO2/C/PEDOT:PSS nanocomposite presented in this work delivered an electrochemical performance comparable to its published counterparts which are obtained by more sophisticated or hazardous methods and with expensive components.

An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.

We propose a resolution enhancement scheme using optical I/O multiperiod transfer functions of NOLMs for ultrafast low-resolution electrical A/D converters (ADCs). This scheme can provide an 8-bit ADC with the effective-number-of-bits of 7.86 bit by combining 8-period optical transfer functions and three 5-bit electrical ADCs. We investigate the performance of ADC about effective resolution, the nonlinear error and missing code due to the resolution of low-resolution ADCs and the number of output bits of the resolution-enhanced ADC.

We introduce the interleaved timing recovery (ITR) technique, with the objective of compensating sampling time errors in interleaved arrays of analog to digital converters (ADC) in high-speed communications receivers. When combined with interleaved automatic gain control (IAGC) and offset compensation (IOC), also discussed, this technique effectively compensates the most important components of fixed pattern noise, an impairment of interleaved ADCs that limits their performance and applicability. This technique exploits functions that are already present in the receiver. By modifying these functions, they can be used to compensate the impairments. This technique compares favorably in terms of performance and hardware complexity with previously known analog and digital calibration techniques. Performance is demonstrated by computer simulation of a 12-bit, 8-way interleaved ADC array whose effective resolution is limited to 6 bits before compensation.

This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new “half-split” feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μm×620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4–6 times, respectively.

A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.

High dynamic range (DR) readout circuits with an intentional offset fully differential output correlated double sampling (CDS) programmable gain amplifier (PGA) and a 14-bit differential input range two-step scaled-reference successive approximation register (SAR) analog digital converter (ADC) are proposed in this paper. The PGA is designed to add an intentional offset to prevent the circuits from saturation in the dark–light environment and convert single-ended and unipolar sensor voltages into a differential and bipolar form for a following-up fully differential input range ADC to improve DR of the readout circuits. The SAR ADC composes 7-bit complementary capacitor array to realize 14-bit differential resolution. Scaled reference buffers with self-calibration operation is presented to work in with the SAR ADC. The PGA and ADC work in pipeline mode to increase the frame rate. The 14-bit readout circuits operating at 600 kSps are integrated in a CMOS image sensor (CIS) with 160 × 190 pixel number, 3000 frame/s (fps) and 25 μm × 25 μm pixel pitch for remote sensing. It is verified using 180 nm CMOS process. The measurement results show that the SNR and SNDR of the prototype ADC is 73.90 and 73.01 dB respectively. The referred input noise of the readout circuits is 117 μVrms. A single column readout circuit consumes 2.48 mW under 3.3 V supply voltage. The figure of merit (FoM) of the CIS is 198 μV × nJ.

Infrared focal plane array (IRFPA) with digital read out interface is a key sign of the third generation IRFPA, which plays an important role in the reliability and miniaturization of infrared systems. A readout integrated circuit (ROIC) of IRFPA with digital readout interface based on dual ramp single slope (DRSS) analog to digital converter (ADC) architecture is presented in the paper. The design is realized using shared ADCs in column-wise and these ADCs are consisted of simplified DRSS architecture and shared units. Sample, conversion and readout are proceeded simultaneously in order to adapt large scale and high readout frame rate application. This circuit also shows many advantages, including small area and low power consumption. Simulation result shows that this architecture can be expand to 320×256 pixel array with a frame rate of 100 frames per second or a larger size whit lower frame rate, the quantized resolution of this circuit is 12 bit, and the analog power consumption is only 17μw per ADC.