Design of a 10 Bit Low Power Split Capacitor Array SAR ADC

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

This paper presents a new single channel 6-bit 900MS/s asynchronous binary search analog to digital converter (ADC). The proposed ADC works based on binary search principle like the Successive Approximation Register (SAR) ADC. Compared to SAR ADC the speed is improved significantly adopting two design techniques. By implementing the binary search in an open loop configuration using asynchronous clock generation the delay in the feedback path of the SAR ADC is relaxed significantly. Moreover in the proposed asynchronous binary search ADC two bits are resolved in each stage of the ADC. By resolving two bits in each stage the proposed ADC can operate twice as fast as conventional asynchronous binary search ADCs. The proposed single channel 6-bit 900MS/s ADC was designed in 90nm CMOS process. Simulation results show that the proposed ADC reaches a peak SNDR of 35.82dB consuming 4.33mW from a single 1.2V power supply. It achieves of 95.3fJ/conv.code FoM.

This paper presents an 8-bit 100KS/s successive approximation register (SAR) analog-to-digital convertor (ADC) in SMIC 0.13 µm 1P8M process for biomedical applications. This ADC is implemented with sub-circuits consuming no static power, thereby preserving the desired low power characteristic. According to the measured results, the SAR ADC has a signal-to-noise distortion ratio (SNDR) of 49.2 dB, and the spurious free dynamic range (SFDR) of 63 dB for a 9.37 kHz full-scale input sinusoidal wave at a 100 kHz sampling rate. The effective number of bit (ENOB) is 7.8 bits. The differential nonlinearity (DNL) is in the range of −0.15/+0.15 LSB whereas the integral nonlinearity (INL) is within −0.35/+0.23 LSB. The total power is 3.2uW and the figure of merit (FOM) is 143 fJ/conversion-step.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

Energy consumption is very critical for environmental monitoring using wireless sensor networks, thus, every block must be designed to consume low energy to be within the limited energy budget of a sensor node. In the context of improving the power efficiency of the analog-to-digital converter (ADC), for this specific application, successive approximation register (SAR) ADC is the best architecture to use. In addition, coarse-fine technique has been proven to reduce power consumption in SAR ADCs. However, design considerations involving the coarse ADC bit allocation are important but not discussed in literature. These includes the following: trade off between resolution of the coarse stage and the accuracy of the ADC; trade off between the energy consumption, accuracy and speed of the comparator block; and trade off between energy consumption and accuracy of different switching schemes for the digital-to-analog (DAC) block. This project produced models of these trade-offs, provided a methodology in designing coarse-fine SAR ADCs, implemented two ADCs in the schematic level: the one with the lowest energy consumption; and the one with the highest Schreier figure of merit (FoMs), and implemented the ADC with the lowest energy consumption in the layout level. Optimization using the MATLAB model in the DAC lead to k = 4 which gives the lowest power and k = 3 which gives the highest Schreier FoM. Schematic implementation at 50kSps of k = 4 and k = 3 gave: 2.201pJ and 2.3617pJ switching energy; 9.2 and 9.3 ENOB; and 170.96 dB and 170.72 dB Schreier FoM, respectively. This project was also able to match the trends of the models to the simulations although there are deviations of values. However, ENOBs fall within the target range of ENOBs.

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with 0.18μm complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.

This paper proposes a high speed and low power 6 bit flash Analog to Digital Converter (ADC) architecture. It comprises of a simple two-transistor based Threshold Inverter Quantizer (TIQ) comparator, modified sample and hold circuit; and ROM encoder. The area and power consumed by the overall ADC architecture is reduced since the comparator transistor count is minimized to two. Existing non-clocked comparators are redesigned and analyzed for appropriate comparison with the proposed comparator. The 6 bit flash ADC consumes a total power of 8.8 mW at an operating speed of 2 GHZ while a single two-transistor based TIQ comparator consumes 0.8679 nW power and has a propagation delay of 46.31 ps for a supply voltage of 1.8 V. The design is implemented in Cadence Virtuoso analog design environment using 180 nm CMOS technology.

We propose a hybrid Analog to Digital Converter (ADC) combined with the first-stage as a first-order feedforward incremental (FF I-) ADC and the second-stage as a SAR (Successive Approximation Register) ADC as high-precision and high-speed ADCs. As a result of simulation, the proposed hybrid ADC correctly converts data even if capacitance in FF path of the first-order I-ADC has 10% error.

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal-oxide-semiconductor technology and occupies an active area of 0.068 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step.