Background capacitor mismatch calibration for pipelined ADC

The paper deals with a novel 12-bit low power switched-capacitor (SC) pipelined analog-to-digital converter (ADC). The problems caused by using of SC technique are compensated or roughly attenuated by means of combination of well-known analog-domain techniques and new digital background calibration technique. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches the fully differential circuitry was utilized. The special op-amps and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the op-amps was taken into account too. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs). It is a histogram-based technique and called the correction with histogram of decision points (CHDP). In this method, the capacitor mismatch and residue amplifier gain error and nonlinearity are corrected by estimating the output code of decision points in the residue characteristic. In order to achieve adequate points, the threshold level of sub-ADC is changed and to increase the estimation accuracy, an algorithm named the mapping histogram is presented. CHDP does not require any special analog circuit and its digital logic is simple. Behavioral simulation results of a 12-bit 100 MS/s pipelined ADC indicate that the proposed calibration scheme improves signal-to-noise and distortion ratio and spurious free dynamic range from 34.1 and 35 dB to 68.2 and 75.8 dB, respectively, while needing about $1.5\,\, {\times } \,\, 10^{6}$ samples for the calibration of five stages.

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.

Testing high resolution DACs: A contribution to draft standard IEEE P1658

This paper presents a digital background timing-skew calibration technique with high accuracy and bandwidth in time-interleaved (TI) analog-to-digital converters (ADCs). Compared with other calibration works, it features three highlights. Firstly, the proposed DCSD-based step-by-step and grouping calibration scheme can effectively improve the correction accuracy by minimizing the root mean square (RMS) value of the detected timing skews. Secondly, the linear compensation for a 13-taps FIR filter and the decimation-calibration-interpolation working pattern are used to expand the calibration effective bandwidth to the whole first Nyquist zone from different perspectives. Thirdly, the binary search is employed, instead of LMS algorithm, in order to meet the compensation requirement for FIR filter and improve the convergence speed and accuracy significantly in timing-skew detection. As a result, the proposed technique achieves the widest calibration bandwidth and higher accuracy compared to other fully digital calibration techniques while having the great convergence speed. Simulation model in MATLAB and FPGA-based hardware verification are employed to demonstrate its significant improvement on the performance and hardware overhead of the TI-ADCs. Finally, the proposed technique is employed in a 10-bit 2.5 GS/s 4-way TI-SAR ADC fabricated by standard CMOS 28nm process. The measurement results show that with the proposed technique, the SFDR and SNDR are improved by 18.9 and 17.9 dB at Nyquist frequency, respectively.

We introduce the interleaved timing recovery (ITR) technique, with the objective of compensating sampling time errors in interleaved arrays of analog to digital converters (ADC) in high-speed communications receivers. When combined with interleaved automatic gain control (IAGC) and offset compensation (IOC), also discussed, this technique effectively compensates the most important components of fixed pattern noise, an impairment of interleaved ADCs that limits their performance and applicability. This technique exploits functions that are already present in the receiver. By modifying these functions, they can be used to compensate the impairments. This technique compares favorably in terms of performance and hardware complexity with previously known analog and digital calibration techniques. Performance is demonstrated by computer simulation of a 12-bit, 8-way interleaved ADC array whose effective resolution is limited to 6 bits before compensation.

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digital circuits, and is applicable to both single-bit and multibit-per-stage architectures. Simulations with a 15-stage, 1.5-bit-per-stage pipelined ADC with capacitor mismatch of sigma = 0.25% in each stage show that the technique improves signal-to-noise-distortion ratio from 62 dB (10 bits) to 94 dB (15.4 bits).

Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analog-converter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then applied to a fine and a coarse ADCs through two paths on the load board, at the same time. For postprocessing in on-chip processor, the correlation equations between the dynamic nonlinearities of sub-DACs/ADCs and the aforementioned loopback responses are simultaneously solved to predict the dynamic nonlinearity for each of a DAC and an ADC. Simulation and hardware measurements verified that the proposed technique can be practically used for production testing, by showing less than 0.28-dB and 0.55-dB of the prediction errors, respectively.

A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC's input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC's coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC's fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC's output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.

System control and the collection of analog signals are fundamental tasks in many embedded computer systems such as are found in automotive, communication, and sensor network domains. Often latency is critical and FPGAs are an attractive alternative. Traditionally, external ADC (analog to digital converter) chips have been used for analog to digital signal conversion and transfer of the digital signals to the FPGA(s). In large-scale quantum system experiments, the implementation of this classic control infrastructure is a challenge. In particular, the FPGA-based control system must work in a liquid helium environment at about 4°K. To improve the system's reliability, we need to integrate multiple lanes of soft core ADC directly into the FPGA. In this paper we propose a method of building high-speed ADCs with time to digital converters (TDCs). The experimental results show that the ADCs can achieve a sampling rate of 100Msa/s with a 6-bit resolution for signals ranging from 0 to 3 V. In our design the ADC uses primarily the ISERDES logic of a Xilinx FPGA plus a small number of CLBs. Our design can integrate 24 lanes of soft-core ADCs into a Xilinx XC7A100t-2csg324 FPGA.

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing code elimination. It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both the static and dynamic performance.