Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters

High dynamic range (DR) readout circuits with an intentional offset fully differential output correlated double sampling (CDS) programmable gain amplifier (PGA) and a 14-bit differential input range two-step scaled-reference successive approximation register (SAR) analog digital converter (ADC) are proposed in this paper. The PGA is designed to add an intentional offset to prevent the circuits from saturation in the dark–light environment and convert single-ended and unipolar sensor voltages into a differential and bipolar form for a following-up fully differential input range ADC to improve DR of the readout circuits. The SAR ADC composes 7-bit complementary capacitor array to realize 14-bit differential resolution. Scaled reference buffers with self-calibration operation is presented to work in with the SAR ADC. The PGA and ADC work in pipeline mode to increase the frame rate. The 14-bit readout circuits operating at 600 kSps are integrated in a CMOS image sensor (CIS) with 160 × 190 pixel number, 3000 frame/s (fps) and 25 μm × 25 μm pixel pitch for remote sensing. It is verified using 180 nm CMOS process. The measurement results show that the SNR and SNDR of the prototype ADC is 73.90 and 73.01 dB respectively. The referred input noise of the readout circuits is 117 μVrms. A single column readout circuit consumes 2.48 mW under 3.3 V supply voltage. The figure of merit (FoM) of the CIS is 198 μV × nJ.

Testing high resolution DACs: A contribution to draft standard IEEE P1658

A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC's input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC's coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC's fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC's output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

This paper presents an ultra-low voltage and power efficient 10-bit hybrid successive-approximation register (SAR) analog-to-digital converter (ADC). To reduce the total amount of capacitance and relieve requirement of comparator, we propose a hybrid architecture composed of coarse and fine conversions by 7-bit SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated by coarse ADC and converting it to time-domain, the fine ADC detects the least three bits with 0.5-bit redundancy by Vernier delay structure. At 250KS/s and Nyquist rate input, the ADC prototype fabricated in 90nm CMOS consumes 200nW at 0.4V supply. It achieves a SNDR of 53.7db and a resulting FoM of 2.02-fJ/conv.-step.

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 ?m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.

In this paper, we study on the automatic gain control (AGC) scheme for pulse amplitude modulation (PAM) with 1.8-V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital converter (ADC) analog-to-digital converters (ADCs) by TSMC 0.18-um CMOS process. For M-PAM networked control systems, this design investigate the problem of AGC schemes under the assumption that applied ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation are used at the receiver end. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic on robotic wireless control system. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization. For of the fixed threshold ADCs, and altering the gain to ADC input, we propose an algorithm based on ADC output's distribution-function to adjust the gain of the amplifier in front of the ADC.

A new digital background calibration technique to compensate the capacitor mismatch in pipelined analog-to-digital converters (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to global gain error. A simple modification to the conventional MDAC allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC. This method does not produce any limitation of the ADC in terms of speed or input dynamic range.

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

High-speed high resolution analog-to-digital converter (ADC) is the key design blocks in mixed-signal chip design since the ADC is an interface between digital signal processing systems and the analog world. With the rapid advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power ADCs that can be realized in a mainstream deep sub-micrometer CMOS technology. On the other hand, since analog circuits tend to be sensitive to fluctuations in temperature and the fabrication process, circuit designers are forced to allow for a wide margin to ensure the desired operation of all the chips under various conditions. Therefore, if the margins can be minimized, both reduction of power dissipation and a higher yield in mass production can be achieved. To tap onto the waves of the rapid booming wireless communication markets, high resolution and high speed A/D converter is required at very low power consumption. Providing the wanted resolution at the required speed for the minimum power consumption and silicon cost is what's driving the use of specific A/D architectures [1]. Architectures that have been applied include flash, subranging, successive approximation, sigma-delta and pipelined. Each of these architectures has their specific advantages and drawbacks. Pipelined architecture poised as a suitable candidate since the power consumption will be an order of magnitude better comparing to flash ADC, subranging ADC, successive approximation ADC and oversampling ADC. Moreover, a correction algorithm can be employed to compensate for the errors in the sub-ADC. Shooting for even higher speed, parallelism is required to be incorporated into pipelined structure. Hence, in this work, a feasibility study of a novel subranging pipelined A/D converter with 100 MS/s and 8-bit resolution is conducted. This research describes the design of a 8-bit 100 MS/s subranging pipelined analog-to-digital converter(ADC) suitable for wide-range applications. To achieve the wide-range performance, this work purposes a novel architectural design at both system and circuit levels. At the device level, device modeling and active components characterisations are carefully studied. Thin gate oxide, NFET is fabricated in Chartered 90nm CMOS process. The results showed that the models used in SPIC simulation correlate well with the measured results except at the end of high VDD where breakdown is seen in the measured results but not during simulation. At the circuit level, a 3-bit coarse ADC and a 6-bit fine ADC are developed. Logic designs are also carried out. At the system level, this work investigates the effects of ADC design parameters such as DNL and INL in the static DC aspects and SFDR and ENOB in the dynamic AC aspects. A top-down design methodology is adopted in this work. The behavioral modelling results verify the success of the proposed architecture. The simulation results showed that the designed ADC is able to achieve a 7.4 effective bits out of 8 bit resolution.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BISTn1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BISTn2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.

To recover the analog voltage at the input of an analog-to-digital converter (ADC) from its digital output, one needs to know at least the ADC gain and offset. For high-accuracy measurements, it is necessary to estimate the actual values of these parameters since they are usually different from the ideal values (one and zero, respectively). This estimation inevitably has an uncertainty, which contributes to the uncertainty of any measurement made with the ADC. Here, the precision of gain and offset error estimators, based on the histogram method for ADC testing is analyzed. The “terminal based” and “independently based” definitions are compared, both through simulation and experimental evaluation. Our conclusion is that, in typical conditions, the “independently based” definition is more precise.

Digital-to-analog converter (DAC) circuit component errors create non-uniform quantization code widths and nonlinear distortion in the DAC's output. In this project, a low complexity 8-bit digital-to-analog converter with partial randomization dynamic element matching (DEM) technique is designed to eliminate pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion in high-resolution DACs. The benefit of this technique is that it gives significantly reduced hardware complexity with no reduction in performance. Simulation results show that nonlinear distortion is greatly suppressed with partial randomization DEM, which offers considerable additional reduction in hardware complexity. In conclusion, this study showed another technique which intends to increase the accuracy and spectral purity of the output signal in data converters.

This brief presents a low-power CMOS image sensor with 14-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to reduce the power consumption and the area. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of 6 bits rather than 14 bits. The multiple sampling also suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the 0.13-μm CMOS process. The measurement results show that the temporal noise is 82.7 μVrms, and the power consumption is 55.1 μW for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and the TS calibration method, the proposed ADC achieves the column fixed-pattern noise of 0.98 LSB and a differential nonlinearity of +0.99/-0.90 LSB.