A fast correlation based background digital calibration for pipelined ADCs

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.

A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors. A two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise (PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing amplifiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V} _{\rm PP} $</tex></formula> ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V} _{\rm PP}$</tex></formula> two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2 in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.

Implementation of photonic analog-to-digital convertor (ADC) using an optimal way of information parallelizing at the level of circuit solutions can significantly improve the performance of the total system (signal source - ADC - computing device). Traditional approach for fast photonic ADC uses processing every time-neighbor sample of input signal by its own channel. For the input signals with limited bandwidth, another approach can be used, in which every input signal spectral interval is processed by its own channel, and the width of the spectral interval is adjusted with the performance of an electronic ADC used for digitizing. In many cases, output signals of electronic ADCs are sufficient for obtaining necessary information from the input signal without joint processing of the output signals of all channels; otherwise, outputs of all channels can be Fourier-processed and concatenated to get complete spectrum of a wideband microwave input signal. For realization of this scheme, a mode locked stable laser together with an amplitude modulator and two combs of narrow band optical filters can be used. Alternatively, a mode locked laser can be replaced with a continuous wave (CW) laser together with a number of optical modulators. Performance capabilities for signal ADC using spectral intervals are estimated. Parameters for optimal system operation are derived. It is shown that, for modern optical elements, 8-10 effective bits can be achieved in the digitized signal.

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

В настоящее время для измерения среднего квадратического значения (СКЗ) применяются преимущественно цифровые методы. Реализация данных методов предполагает использование аналого-цифровых преобразователей (АЦП) для получения отсчетов входного сигнала в цифровом виде. Функция преобразования (ФП) реального АЦП имеет аддитивные, мультипликативные и нелинейные составляющие погрешности. Данные составляющие имеют различные коэффициенты влияния на погрешность измерения СКЗ. Показано, что аддитивная составляющая практически не влияет на погрешность измерения СКЗ, а мультипликативная составляющая погрешности ФП АЦП линейно связана с погрешностью измерения СКЗ. Для случая синусоидального и полигармонических входных сигналов получены аналитические оценки влияния нелинейности ФП АЦП на погрешность измерения СКЗ. Достоверность выражения для случая синусоидального входного сигнала подтверждена результатами имитационного математического моделирования, выполненного в программном пакете Matlab. Выполнено исследование влияния амплитудного значения входного сигнала и его начальной фазы на погрешность измерения СКЗ, вызванную нелинейностью ФП АЦП. Для оценки эффективности предлагаемой методики путем имитационного математического моделирования получены оценки погрешности измерения СКЗ для случая АЦП ADS8372 (построен по архитектуре последовательного приближения) и ADS1610 (построен по сигма-дельта архитектуре). Производитель обоих рассматриваемых АЦП – компания Texas Instruments. Проанализированы аддитивные, мультипликативные и нелинейные составляющие погрешности рассматриваемых АЦП. Показано, что предлагаемая методика оценки погрешности измерения СКЗ, вызванная нелинейностью АЦП позволяет сверху оценить погрешность измерения СКЗ, вызванную нелинейностью ФП АЦП. Однако данная оценка погрешности завышена относительно результатов имитационного моделирования. Abstract – Currently, to measure the root mean square values (RMS) are commonly used digital methods. The implementation of these methods involves the use of analog-to-digital converters (ADC) for receiving input signal samples in digital code. Transform function (DFT) of a real ADC contains additive, multiplicative and nonlinear components of the error. These elements have different coefficients of influence on RMS measurement error. It is shown that the additive component virtually does not affect the accuracy of the RMS measurement, and a multiplicative component of the ADC error is linearly related to the RMS measurement error. For the case of polyharmonic and sinusoidal input signals derived the analytical expression showing the effects of the ADC nonlinearity to the RMS measurement error. The reliability of the expressions for the case of sinusoidal input signal is confirmed by results of mathematical simulation performed in the software package Matlab. The research of the influence of the amplitude value of the input signal and the initial phase of the RMS measurement error caused by the nonlinearity of the ADC is performed. To assess the effectiveness of the proposed method by mathematical simulation the estimates of RMS measurement error for the case of ADC ADS8372 (built on the architecture of successive approximation) and ADS1610 (built on the Sigma-Delta architecture). The manufacturer of both the considered ADC is the company Texas Instruments. Analyzed the additive, multiplicative and nonlinear components of the error of the considered ADC. It is shown that the proposed method of estimation of RMS measurement error caused by the nonlinearity of the ADC allows the top to assess the RMS measurement error caused by the nonlinearity of the ADC. However, this error estimate is overstated relative to the simulation results.

The paper presents a method for increasing the resolution of parallel analog-to-digital converters (ADCs) with time compression of signals. It is established that analog-to-digital conversion of signals in parallel ADCs with time compression of output signals is performed in separate channels with non-identical bandwidths. Ultimately, this leads to a decrease in resolution when converting input signals. The difference in the bandwidths of parallel ADC channels is due to the features of the sample and store circuits (SSCs), which are installed at the inputs of each ADC. SSCs are necessary to reduce dynamic errors that arise when discretizing time-varying analog signals. The functioning of SSCs is based on the principle of fixing the instantaneous value of the input signal for the time required for further conversion in the ADC. The input circuits of SSCs can be represented as low-pass filters, in which there is a spread of the parameters of resistors and capacitors that determine the bandwidth of the i-th ADC channel. The passband adjustment in each ADC channel is carried out by switching resistors in the input circuits of the converter. To reduce the errors of non-identity of the passbands, it is proposed to introduce a reference additional ADC (АADC), which operates with a lower sampling frequency. In the operating mode, one of the ADC channels is calibrated. At the same time, the reference АADC operates with a sampling frequency that allows it to operate in phase with one of the working ADCs in each conversion cycle. A structural diagram of a parallel ADC (PADC) based on time compression of signals with correction of the passbands of individual ADC channels has been developed. The PADC operates in two modes: calibration and working with correction. In the calibration mode, a sinusoidal signal is supplied to the inputs of all PADC channels from the output of the test signal generator through an analog switch. The array of digital data from the output of the ADC is accumulated in a buffer storage device. Then, the accumulated array is fed to a computer via an interface adapter and a USB bus, where the errors of non-identity of the bandwidths of the ADC channels are calculated. Each ADC channel contains a digital-to-analog converter at the input, which performs the function of a digital potentiometer for the input signals of the SSC. The calculated transfer coefficients from the outputs of the control unit are fed to the corresponding ADC channels. Analysis of the ADC efficiency showed that by adjusting the bandwidths of individual channels of a 12-bit PADC, it is possible to improve the resolution in the low-frequency band by 0,5 bits, and in the high-frequency band by 1,9 bits.

This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18-/spl mu/m CMOS achieves a conversion rate exceeding 1.6 GSample/s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS/s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. This includes lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADC is required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset error in its transfer function, which will lead to fix pattern noise. Correcting these gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. Therefore, a technique to minimize the effects of gain error in a delta-sigma modulation ADC for CMOS image sensor is discussed.

This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the coarse bits (MSBs), is required for the modulator and LSBs are fed back as a time-modulated pulse (TMP). Therefore, high quantization resolution is achieved without increasing the front-end DAC complexity. Additionally, a new data weighted averaging (DWA) technique is proposed which not only suppresses the mismatch between the unit elements of the MSB DAC, but also aims to average out the gain error between the MSB and LSB DACs. Therefore, the possible quantization noise leakage is drastically reduced. Detailed mathematical models as well as comprehensive simulation results are provided to prove the efficiency of the proposed structure.

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs' parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.

This paper presents a fast phased array calibration method which significantly reduces the number of antenna under test (AUT) amplitude and phase setting states. Multiple measuring probes are introduced to record transmission coefficients as AUT works at different states. A coefficient matrix with a small condition number is constructed to calculate the initial excitation coefficients of each antenna element. Simulation results show that the coefficient matrix condition number can be reduced to 1 by optimizing the geometry of the measurement system. When the signal-to-noise ratio is higher than 18dB, the amplitude error of the calibration result is less than 0.5dB and the phase error is less than 20 degrees in the optimal conditional number configuration. This method effectively reduces the measurement time for the phased array calibration and improves the stability of the calibration system.

By applying information theoretic concepts to analog-to-digital convertor (ADC) design, we have created a mathematical framework from which the fundamental limit for the resolution-bandwidth product of any ADC may be derived. We found the surprising result that the limiting resolution of any ADC is proportional to oversampling-ratio (OSR), as opposed to widely-held belief that the resolution is proportional to \(log_2(OSR)\), a dramatic increase in the achievable resolution. This result, which resembles Shannon’s well-known result for the capacity of a communication channel, represents a paradigm shift in our understanding of data conversion methods and provides encouragement that new methods may be found. Furthermore, to achieve this theoretical limit, the internal analog modulator (or filter) of an ADC should be a chaotic system, so that both small as well as large changes in the input signal cause large (but bounded) deterministic changes at the output of the modulator - analogous to the “Butterfly effect”. This led us to discover a new class of ADCs, which we call TurboADC’s, that can trade off resolution for bandwidth on the fly, keeping their product equal to the fundamental information theoretic limit. These designs impose modest requirements on the analog front-end resources and power at the expense of greater complexity in the back-end decoder. A discrete-time TurboADC proposed here is a hybrid of a 1st order Delta-Sigma modulator and a Cyclic ADC, with the best features of both designs - oversampling, noise shaping, and simplicity from the Sigma-delta ADC approach and fast half-interval searching from Cyclic ADC’s. Simulations of the proposed TurboADC confirm our finding that the resolution of an ADC may approach fundamental limit of OSR bits within the baseband.

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digital circuits, and is applicable to both single-bit and multibit-per-stage architectures. Simulations with a 15-stage, 1.5-bit-per-stage pipelined ADC with capacitor mismatch of sigma = 0.25% in each stage show that the technique improves signal-to-noise-distortion ratio from 62 dB (10 bits) to 94 dB (15.4 bits).

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2.

We have designed single-bit comparators and multi-bit flash analog-to-digital converters (ADCs) using three flavors of periodic comparators; one flavor uses a differential “quasi-one-junction” SQUID (DQOS) comparator, the second use a differential SQUID wheel comparator (DSW) and the third uses a symmetric differential SQUID wheel comparator (SDSW) with time-interleaved clocks. We have also developed a new performance analysis scheme that enables full reconstruction of input signal using a single-bit comparator. The signal is reconstructed based on multiple beat frequency measurements that track the position of the comparator thresholds in response to a dc offset to the input signal. In addition, to eliminate the frequency dependent distortions resulting from impedance mismatches over wide bandwidths, the signal and clock distribution network have been optimized using EM simulations. For distributing the clock signal to the multi-bit comparators, a 50 Ω coplanar transmission line has been designed. Test results for a 1-bit DSW comparator demonstrates a performance of 4.5 bits of resolution in Gray code for a beat frequency test using a 20 GHz input signal and 5.3 bits for 10 GHz input. 4 and 8-bit versions of the flash ADC with a DQOS comparator and a 3-bit time-interleaved ADC using the SDSW comparator have also been designed. The DQOS ADC has been tested up to 25 GHz input signal frequency with performance of 4.3 bits of resolution in Gray code for 19.7 GHz input signal. The time-interleaved ADC performance is 4.3 bits for a 15 GHz beat frequency test with an effective sampling rate of 30 GHz.