A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

Low-power microarchitecture designs of Viterbi decoder are considered one of the on-demanding issues in Very Large-Scale Integration (VLSI). Viterbi decoders consume 35% of the power and 76% of the complexity in digital communication schemes, e.g., IEEE 802.11 a/g WLAN schemes. Development of Viterbi decoder itself reduces dramatically system complexity; the decoder has a source of power sink unit which rises in Add Compare-Select (ACS) unit. Various levels of development exist in VLSI such as architecture, microarchitecture, circuit, and transistor. ACS is structured of adder, comparator, and selector, so microarchitecture development of ACS unit intends one of these superior blocks. Adders in VLSI designs have a tremendous interest as they are the kernel of any digital system so enhancing this basic building block, which is used over and over, influences system specification. This paper targets different microarchitectural approaches to shrink the power of this unit which enhances overall system specification. Microarchitecture development encompasses using another block instead of the existing one or repositioning current blocks. In this review paper, comparisons of different parallel adders are presented to achieve low consumption power while obtaining high-speed operation of the addition, and an arrangement of ACS blocks to reduce the complexity of the decoder is also provided.

The mobile video, audio and data services can be provided by a DMB (digital multimedia broadcasting) system based on Eureka-147 standard in Korea. In Korea the S-DMB and the T-DMB use the different systems each other. For the both of the satellite and the terrestrial DMB services using the same platform, an integrated RF module is required. In this paper -we show the design of an integrated RF tuner module which includes a L-band down-converter and a band III tuner and a S-DMB tuner, and show the measured results of an integrated RF module for T-DMB that give an IF output of 38.912 MHz and a VCO of 220.32 MHz to 282.72 MHz with PLL setup

Area efficient turbo decoder structures are needed in 3G receivers. Typically, max-log-MAP decoders are used as component decoders. In this paper, it is shown that all the computations of the max-log-MAP algorithm can be carried out with slightly modified add compare select (ACS) units. All the required computations of the max-log-MAP algorithm are analyzed and they are mapped to the proposed ACS units (ACSU). A set of four ACSUs is multiplexed to carry out the computations. With the presented method, the structure of the max-log-MAP decoder is simplified and the computing resources are shared economically

A novel asynchronous data-path design is described. Circuits for the asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed. An asynchronous data-path ACS (add-compare-select) for a Viterbi decoder is formed. The performance of the 4-bit ACS is analyzed with a novel method based on a multi-delay model. The results of performance analysis of the asynchronous 4-bit ACS show that the average case response time of 6.81 ns is only 84% of the worst-case response time, 8.08 ns. It reveals that the asynchronous data-path has some performance advantages over the synchronous one.

이 논문에서는 계층변조를 적용하는 AT-DMB (advanced terrestrial digital multimedia broadcasting) 시스템에 적용할 수 있는 블라인드등화 기법을 제시하고 그 성능을 살펴본다. AT-DMB 시스템은 기존 T-DMB의 DQPSK (differential quadrature phase-shift keying) 신호와 역방향 호환성을 보장하고 더 높은 데이터 전송률을 지원하기 위해 16-QAM (quadrature amplitude modulation) 계층변조 방식을 적용한다. 이 결과 SNR (signal to noise ratio)에 따라 기존 T-DMB 심볼과 추가된 심볼은 서로 다른 판정오율 (decision error rate)을 가진다. 따라서 판정한 신호로부터 채널을 추정할 때 판정오율이 낮은 선순위 심볼과 판정오율이 높은 후순위 심볼의 신뢰도에 따라 다른 가중치를 줌으로써 판정치의 전체적인 신뢰도를 향상시킬 수 있다. 이 논문에서는 계층변조에 따른 비트 오율(bit error rate) 성능의 악화정도를 분석하고, 모의실험을 통해 판정신호의 신뢰도에 따라 가중치를 주는 제안방식이 가중치를 주지 않은 경우에 비해 비트 오율 성능이 향상됨을 확인하였다. In this paper, we propose a blind equalization method for advanced terrestrial digital multimedia broadcasting (AT-DMB) systems which use hierarchical modulation. The AT-DMB system adopts hierarchical 16-ary quadrature amplitude modulation (16-QAM) to ensure backward-compatibly with the differential quadrature phase shift keying (DQPSK) signal of the legacy terrestrial digital multimedia broadcasting (T-DMB) systems and to support higher transmission rate. Due to the hierarchical modulation, the conventional T-DMB signal and the additional signal have different error rate at same signal to noise ratio (SNR). By weighting the decided symbols differently according to the reliability of the symbols, i.e., high priority symbol with low error rate and low priority symbol with high error rate, we can improve the channel estimation accuracy. In this paper, we analyze SNR loss by hierarchical modulation and confirm it through simulations. Moreover, through simulations, we verify that the proposed weighting method improve BER compared to the no-weighting method.

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6 K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5 mW at 100 MHz.

Dynamic partial reconfigurable Viterbi decoder for wireless standards

In recent years, multimedia content broadcasting via satellite has attracted increased attention. The satellite digital multimedia broadcasting (S-DMB) system has emerged as one of the most promising alternatives for the efficient delivery of multimedia broadcast multicast service (MBMS). The design of an efficient radio resource management (RRM) strategy, especially the packet scheduling scheme, becomes a key technique for provisioning multimedia services at required quality of service (QoS) in S-DMB. In this article, we propose a novel cross-layer packet scheduling scheme that consists of a combined delay and rate differentiation (CDRD) service prioritization algorithm and a dynamic rate matching (DRM)-based resource allocation algorithm. The proposed scheme considers multiple key factors that span from the application layer to the physical layer, aiming at simultaneously guaranteeing diverse QoS while utilizing radio resources efficiently under the system power and resource constraints. Simulation results demonstrate that the proposed cross-layer scheme achieves significantly better performance than existing schemes in queuing delay, jitter, and channel utilization.

This paper presents a new self-resetting CMOS design for an add-compare-select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.

This paper describes the hardware design of a high speed Viterbi decoder for the IEEE 802.11a Wireless Local Area Networks (WLAN) application. A fully parallel Add-Compare-Select (ACS) and trace-back architecture is presented to achieve the decoding rate up to 54Mbps. Modulation scheme and coding rate dependent quntaization accuracy for soft decision Viterbi decoding is explored and a hardware implementation scheme with run-time configurable bit-length for soft decision is then proposed to reduce the system power consumption.

A 140-Mb/s, 32-state, radix-4, R=1/2, eight-level soft-decision Viterbi decoder has been designed and fabricated using 1.2- mu m double-metal CMOS. The architecture of the add-compare-select (ACS) array is based on a restructuring of the conventional radix-2 trellis into a radix-4 trellis. Radix-4 units, consisting of four 4-way ACS units, process two stages of the constituent radix-2 trellis per iteration. A four-way ACS circuit achieves an iteration delay 17% longer than comparable two-way ACS circuits, resulting in a factor of 1.7 increase in throughput. A ring-based ACS placement and state metric routing topology achieves an area efficiency comparable to radix-2 designs. In a process referred to as pretrace-back, one stage of lookahead is applied to the trace-back recursion, combining two radix-4 trace-back iterations into a single radix-16 iteration based on 4-b decisions. This allows implementation of trace-back using one compact, single-ported decision memory, organized as a cyclic buffer. A 7.30-mm*8.49-mm chip containing 146000 transistors achieves a radix-4 iteration rate of 70 MHz. >

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the minimized method (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

In this paper, we propose a novel multiple symbol differential detection (MSDD) based on symbol error position estimation (SEPE) and compensation for use in terrestrial digital multimedia broadcasting (T-DMB) system. By estimating the symbol error position and compensating for the symbol error using MSDD outputs, it can improve the receive performance of T-DMB system. Also by providing soft-outputs to Viterbi decoder, an additional coding gain can be obtained. Simulation results in the typical urban (TU) channel show that the proposed algorithm is superior to the conventional differential detection (DD) and hard decision based MSDD T-DMB receivers.

In order to improve current transmission capacity of the ancillary data in terrestrial digital multimedia broadcasting (T-DMB) system, the hierarchical modulation is adopted. The hierarchical modulation consists of Higher-priority (HP) data, which is the same as in the legacy T-DMB, and Low-priority (LP) data, which carriers the additional data for the upgrade system, while the backward compatibility is guaranteed. Both QPSK modulation and 4ASK modulation are good candidates for LP data modulation. So in this paper we adopt coherent detection with comb-type pilot arrangement, the Least Squares (LS) estimate of pilot signals and the piecewise-linear interpolation channel estimation. Simulation results show that LP-QPSK provides a better choice than LP-4ASK for achieving a higher data rate in the Advance T-DMB (AT-DMB).KeywordsAT-DMBLP-4ASKLP-QPSKHierarchical modulation