A fault tolerant massively parallel processing architecture

With an increasing number of processing elements (PEs) integrated on a single chip, fault-tolerant techniques are critical to ensure the reliability of such complex systems. In current reconfigurable architectures, redundant PEs are utilized for fault tolerance. In the presence of faulty PEs, the physical topologies of various chips may be different, so the concept of virtual topology from network embedding problem has been used to alleviate the burden for the operating systems. With limited hardware resources, how to reconfigure a system into the most effective virtual topology such that the maximum repair rate can be reached presents a significant challenge. In this article, a new approach using a maximum flow (MF) algorithm is proposed for an efficient topology reconfiguration in reconfigurable architectures. In this approach, topology reconfiguration is converted into a network flow problem by constructing a directed graph; the solution is then found by using the MF algorithm. This approach optimizes the use of spare PEs with minimal impacts on area, throughput, and delay, and thus it significantly improves the repair rate of faulty PEs. In addition, it achieves a polynomial reconfiguration time. Experimental results show that compared to previous methods, the MF approach increases the probability to repair faulty PEs by up to 50% using the same redundant resources. Compared to a fault-free system, the throughput only decreases by less than 2.5% and latency increases by less than 4%. To consider various types of PEs in a practical application, a cost factor is introduced into the MF algorithm. An enhanced approach using a minimum-cost MF algorithm is further shown to be efficient in the fault-tolerant reconfiguration of heterogeneous reconfigurable architectures.

Defining a dual role for spare processing elements (PEs) in reliability-challenged processing arrays is the major focus of the paper. The paper also explores a practical way to include reconfiguration hardware in single-package arrays. The implementation of array processor systems may include spare PE's for fault tolerance. These systems typically require a host for fault diagnosis, while the healthy spares sit idle. It is proposed to utilize the idling spare PEs for purposes of fault diagnosis, giving the array the capability of self diagnosis. Fault tolerance must incorporate additional hardware for reconfiguration, and existing plans have not found widespread use in single-package systems due to the extra cost and extra real estate. Multichip modules (MCMs) have the potential to offer fault tolerance with no increase in primary circuit area. It is proposed to contain the reconfiguration hardware in the active substrate of a silicon-based MCM. Further, the switches required for spares coverage can aid in the job of comparison based self-testing. We offer a complete solution to fault-tolerant arrays in the sense that diagnosis, reconfiguration and switching details are all addressed.

Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.

The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, we propose a centralized hardware fault-tolerant network interface (NI) for NoCs based on spatial division multiplexing. Experiments show that the proposed design has better throughput than a non fault-tolerant design with only 18% area overhead. We also introduce an area optimized distributed fault-tolerant NI architecture which provides 50% more throughput than the centralized design for high fault rates.

Currently, using commercial off-the-shelf (COTS) components and constructing parallel system becomes the main way to improve satellite system performance remarkably. System reliability relying on its structure rather than devices makes system fault-tolerant architecture and strategy increasingly important. As centralized fault-tolerant solution has the inherent drawback of single point of failure (SPOF), it can not guarantee system reliability well. Distributed fault- tolerant method, due to its complexity and large overhead, has not been maturely used. In this paper, we propose a new distributed fault-tolerant scheme with high reliability and flexibility, in which an equal symmetric distributed fault- tolerant (ESDFt) architecture is constructed. Based on the structure, functional module framework of system nodes and autonomous fault-tolerant strategy are designed. The ESDFt scheme creates favorable conditions for flexible implementation of system fault tolerance. It utilizes the master election mechanism, which eliminates the risks of SPOF and chooses master node intelligently based on user's configuration, making fault-tolerant complexity and processing overhead flexibly adjustable. The verification and evaluation of ESDFt scheme has been performed on a prototype system. The experiment results prove that ESDFt scheme not only ensures system reliability well, but also enhances system flexibility and practicality at the same time.

Cloud services are one of the most quickly developing technologies. Furthermore, load balancing is recognized as a fundamental challenge for achieving energy efficiency. The primary function of load balancing is to deliver optimal services by releasing the load over multiple resources. Fault tolerance is being used to improve the reliability and accessibility of the network. In this paper, a hybrid Deep Learning-based load balancing algorithm is developed. Initially, tasks are allocated to all VMs in a round-robin method. Furthermore, the Deep Embedding Cluster (DEC) utilizes the Central Processing Unit (CPU), bandwidth, memory, processing elements, and frequency scaling factors while determining if a VM is overloaded or underloaded. The task performed on the overloaded VM is valued and the tasks accomplished on the overloaded VM are assigned to the underloaded VM for cloud load balancing. In addition, the Deep Q Recurrent Neural Network (DQRNN) is proposed to balance the load based on numerous factors such as supply, demand, capacity, load, resource utilization, and fault tolerance. Furthermore, the effectiveness of this model is assessed by load, capacity, resource consumption, and success rate, with ideal values of 0.147, 0.726, 0.527, and 0.895 are achieved.

Upcoming processor architectures support parallel processing on different levels. Multiple processing elements (PEs) run in parallel. The PEs consists of several functional units and the functional units allow sub-word parallelism (SWP), i.e. the parallel execution of operations with low data word width. In this paper, a parameterized mapping of algorithms onto massively parallel processor architectures (PAs) is derived which exploits both parallelism on PA and SWP on PE level. It establishes a correlation between the parameters of the algorithms and the parameters of the PA, which enables optimization strategies with respect to several expense factors of the PA. The design approach is based on the co-partitioning method and the partitioning of data dependencies. Both are used in a hierarchical manner. Besides the parameters of the PA (such as shape, number of PEs, number of sub-words processed in parallel, channels between the PEs, and their delay), the packing instructions for exploiting SWP can be deduced

Fault tolerance is the most imperious issue in the cloud to provide reliable services. Inherent vulnerability to failure hampers the performance and reliability of cloud services. Hence, to achieve reliability, fault tolerance becomes a mandatory feature which is hard to implement due to the dynamic infrastructure and complex interdependencies. Numerous fault tolerance techniques have been developed in the literature to address the challenges of cloud reliability. A recent research survey presented in this paper attempts to integrate the different fault tolerance architecture. This study presents a critical research review on various existing fault tolerance techniques to improve services reliability, availability, and applications execution in the cloud. A comparative analysis, based on different critical metrics like failure prediction, detection strategy, failure history, VM placement, and limitations, of the reviewed framework systems is also included in the paper. This review intends to facilitate the development of the new fault tolerance technique for the cloud environment.

: This report provides a synopsis of research performed in fault- tolerant computing, for the first year of grant AFOSR-84-0052. Also included is a list of publications that have resulted from the research supported by this grant. Additionally, this report reviews the future direction for the continuing research under this grant. In the past year, this effort has focussed on the following problems: (1) Investigation of novel fault-tolerant processor array architectures with the potential of a high degree of defect tolerance, but having low processor and interconnect overhead associated with the fault tolerance mechanisms; (2) Development of realistic models to evaluate the yield, redundancy and performance tradeoffs for the designs. Such models would help establish the viability of these architectures, also enabling them to be compared with other designs in the literature; (3) Development of new and efficient testing strategies, and reconfiguration schemes for their structures; (4) Testable design of large size VLSI memory; and (5) Development of novel sorting networks that can be implemented on a single chip or wafer. Three journal articles were supported during the grant period: 'Synthesis of Directed Multicommodity Flow Networks,' Vol. 14, pp. 213-224 (with A. Stai); 'Fault- Tolerant Multiprocessor Link and Bus Network Architectures, IEEE Transactions on Computers, Vol. C-34, No. 1, January 1985, pp. 33-46; and 'Dynamically Restructurable Fault-Tolerant Processor Network Architectures,' IEEE transactions on Computers (to appear).

Fault tolerance engineering has been advocated as one of the main approaches to ensuring the overall system dependability. The 2nd International Workshop on Engineering Fault Tolerant Systems (EFTS 2007) aims to investigate how fault tolerance mechanisms can be taken into account when engineering complex software systems and to improve our understanding of where and how fault-tolerance should be integrated in the software life-cycle. The focus of the workshop is on developing novel models to be applied at different abstraction levels (requirements, architecture and design models for fault tolerance, together with new implementation schemes), innovative technologies (tools and frameworks for implementing distributed fault tolerant systems) and advanced verification environments (to assess the achieved level of fault tolerance and to evaluate the dependability properties of the systems). Recently there has been a growing interest in the areas directly related and overlapping with fault tolerance, such as self-healing, resilience, self-adaptation and self-management. The topics related to engineering of systems with such properties are in the scope of the workshop as the intention is to improve the current understanding of how fault tolerance engineering can benefit from research on these areas.

This paper presents a method to time share the Processing Elements (PEs) of Runtime Coarse Grain Reconfigurable Architectures (CGRA) among multiple processes being executed concurrently onto the same CGRA. Runtime CGRA architectures time-multiplex the data path, creating a set of contexts for each state. These contexts configure the PEs and the routing resources of the CGRA and are typically loaded every clock cycle. The target architecture in this work is a commercial CGRA IP which is embedded as an IP into complex SoCs. Our proposed method analyzes the PE utilization in each context for multi-process systems running concurrently onto the same CGRA and time shares unused PEs assigned to one process with the other processes running in parallel. Our method reduces the total PE usage and hence the size of the CGRA IP and therefore the cost of the SoC. Results show that our method is extremely efficient and can reduce the PE utilization by up to 20% and on average by 14% and is only 2% worse than the optimal solution, while being much faster.

A nonlinear, nonrecursive, two-dimensional filter has been developed for edge-preserving noise smoothing of images. It can also be beneficial as a pre-processor for data compression purposes. The filter is applied over a 3x3 window of pixels and uses an adaptive threshold. As with all image filters, the computational requirements lead to the utillization of special purpose VLSI hardware for real time implementation. The algorithm is being implemented in VLSI using a systolic array structure and parallel architecture, in which each processing element is assigned to one pixel. The structure of the processing element is very simple: except for some control gates and registers, it contains only a one-bit full adder as the main functional element. The most important feature of the proposed architecture is that the nonlinear operation has been implemented using no more than the simple tools and the silicon area required for a linear convolutional algorithm. Other properties of the above design are: simple interconnection scheme between processing elements and common control circuitry for all the processing elements on a single chip. Due to the topological simplicity of the processing element, arrays of size 16x16 cells per chip are believed to be feasible, using standard CMOS technology.

Since careless driving causes a terrible traffic accident, it is an important subject for a vehicle to avoid collision autonomously. Real-time collision detection between a vehicle and an obstacle will be a key target for the nextgeneration car electronics system. In collision detection, high-computational power is essential not only in coordinate transformation but also in matching operation. In the proposed collision detection VLSI processor, the matching operation is sharply accelerated by using a content-addressable memory which evaluates the magnitude relationships between an input word and all the stored words in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speeds, and each PE performs coordinate transformation at high speeds based on the Coordinate Rotation Digital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 6.48ms.

This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the PEs can be configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that maximum on-chip memory consumption is reduced. To achieve high on-chip memory utilization, the architecture features that the instruction register in each PE is mapped in its local memory space and that the ALU network and the local memory network can be configured independently. Simulation results show that the proposed architecture effectively utilizes both of the SIMD and operation pipeline modes.

The concept, design, and features of a fault-tolerant intelligent robotic control system being developed for Space and commercial applications that require high dependability are described. The comprehensive strategy integrates system level hardware/software fault tolerance with task level handling of uncertainties and unexpected events for robotic control. The underlying architecture for system level fault tolerance is the distributed recovery block which protects against application software, system software, hardware, and network failures. Task-level fault tolerance provisions are implemented in a knowledge-based system which utilizes advanced automation techniques such as rule-based and model-based reasoning to monitor, diagnose, and recover from unexpected events. The two-level design provides tolerance of two or more faults occurring serially at any level of command, control, sensing, or actuation. >